Abstract:
A filter and a filtering method are provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal.
Abstract:
A phase-difference detecting method is for detecting phase difference between a first signal and a second signal of the same frequency. First, generate a detection signal. Next, sample the detection signal respectively according to the first signal and the second signal to obtain a first sample value and a second sample value. Then, determine whether a determination condition that the first and the second sample values are respectively equal to the previous first and second sample values is satisfied. When the determination condition is unsatisfied for the first time, record a delay time of the detection signal as a first time. When the determination condition is unsatisfied for the second time, record a delay time of the detection signal as a second time. Obtain the phase difference between the first signal and the second signal according to the first time and the second time.
Abstract:
A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.
Abstract:
A global positioning System receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the multiplications therefrom for generating the total addition values.
Abstract:
A global positioning system receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the products therefrom for generating the total summation value. Therefore, the correlating circuit having portable process is formed. Moreover, an external memory is used to store the sample digital data for reducing costs.
Abstract:
A method for actuating a system on chip (SOC) includes the following steps. First, determine whether the SOC is connected to a computer system via a communication connection. If no, determine whether a non-volatile memory of the SOC has an initial flag signal. If yes, read correction information stored in the non-volatile memory in response to the initial flag signal and set a corresponding first register of the SOC according to the correction information.
Abstract:
An impedance matching circuit has comparator, counter, two current sources, semiconductor resistance device, and variable MOS impedance device. The current sources are respectively coupled to an internal impedance device and an external impedance device. The comparator has two input terminals and an output terminal. The input terminals of the comparator are coupled to the internal and external impedance devices. The output terminal of the comparator is coupled to the counter. The variable MOS impedance device is coupled between the counter and the semiconductor impedance, and is controlled by the counter. When the voltages of the internal impedance and the external impedance are not matched, the variable MOS impedance device can provide the compensating impedance by adjusting the counting value of the counter.
Abstract:
A power protection device includes a power source switching unit for shutting off the power supply from an AC power source according to an open control signal, a surge voltage protecting unit for outputting the open control signal when a surge voltage occurs, a leakage current protecting unit for outputting the open control signal when a leakage current occurs, and an over-current protecting unit for outputting an open control signal according to a current value when an over-current occurs. The power protection device provides the surge voltage protection, the leakage current protection and the over current protection at the same time.
Abstract:
A hysteresis circuit for use in a comparator having a first and a second transistors as an input stage and a constant current source. The hysteresis circuit comprises a first resistor disposed between a source of the first transistor and the constant current source and a second resistor disposed between a source of the second transistor and the constant current source, and comprises a first and a second current generating means. The first current generating means supplies a current to the source of the first transistor and derives a current out from the source of the second transistor if an output signal of the comparator is a first logic value, while the second current generating means supplies a current to the source of the second transistor and derives a current out from the source of the first transistor if the output signal of the comparator is a second logic value.
Abstract:
A bridge device having data monitoring function is disclosed. The bridge device can be made to be an integrated circuit (IC) chip, so as to be disposed on a circuit board with a USB connector and a UART connector, thereby forming a USB to UART converter. When using the USB to UART converter, the USB connector is connected to a host computer, and the UART connector is connected to an electronic device. As such, the bridge device provides the host computer with at least three virtual COM ports, such that the host computer is able to conduct a data transmission with the electronic device through one virtual COM port. Moreover, during the data transmission, the host computer is also able to hear the transmitted data by way of diverting the transmitted data through the other two virtual COM ports.