公开(公告)号：US11901900B2

公开(公告)日：2024-02-13

申请号：US17843780

申请日：2022-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Kailash Kumar ,  Manoj Kumar

IPC: H03K3/00 ,  H03K3/012 ,  H03K3/3565 ,  H03K3/2893

CPC classification number: H03K3/012 ,  H03K3/2893 ,  H03K3/3565

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.

公开(公告)号：US09442506B2

公开(公告)日：2016-09-13

申请号：US14051631

申请日：2013-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Chieh Huang ,  Tien-Chun Yang ,  Steven Swei

IPC: G05F3/30 ,  H03K3/2893 ,  G05F3/02 ,  G05F3/24

CPC classification number: G05F3/02 ,  G05F3/245

Abstract: A voltage reference circuit with temperature compensation includes a power supply, a first reference voltage supply, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor connected to the second NMOS source and ground. The voltage reference circuit also includes a second reference voltage supply, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor with a drain connected to the source of the fourth NMOS transistor, a source connected to the ground, and a gate connected to the first reference voltage output.

Abstract translation: 具有温度补偿的电压参考电路包括电源，第一参考电压源，第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，连接到第二NMOS源极和地的电阻。 电压参考电路还包括第二参考电压源，第三PMOS晶体管，第四PMOS晶体管，第三NMOS晶体管，第四NMOS晶体管和第五NMOS晶体管，漏极连接到第四NMOS晶体管的源极， 连接到地的源极和连接到第一参考电压输出的栅极。

公开(公告)号：US5796280A

公开(公告)日：1998-08-18

申请号：US795942

申请日：1997-02-05

Applicant: Claudio Tuozzolo

Inventor： Claudio Tuozzolo

IPC: H03K3/2893 ,  H03K17/08 ,  H03K17/082 ,  H03K3/037

CPC classification number: H03K17/0826 ,  H03K3/2893 ,  H03K2017/0806

Abstract: A thermal shut down circuit with built-in temperature hysteresis, comprising first and second transistors configured as a bistable trigger circuit. The two transistors switch either a first or second emitter current through a bias resistor, thereby establishing a voltage hysteresis. By applying a reference voltage to the base of the first transistor, temperature dependent state transitions occur. A buffer transistor coupled to the collector of the second transistor allows the thermal shut down circuit to turn ON or OFF an auxiliary circuit. Thermal communication between the auxiliary circuit and the base-emitter junction of the first transistor allows the thermal shut down circuit to shut down the auxiliary circuit when the temperature exceeds a shutdown temperature, and thermal hysteresis built into the thermal shut down circuit prevents undesirable ON-OFF oscillation of the auxiliary circuit.

Abstract translation: 具有内置温度滞后的热关断电路，包括配置为双稳态触发电路的第一和第二晶体管。 两个晶体管通过偏置电阻器切换第一或第二发射极电流，从而建立电压滞后。 通过将参考电压施加到第一晶体管的基极，发生温度依赖状态转变。 耦合到第二晶体管的集电极的缓冲晶体管允许热关断电路接通或关断辅助电路。 辅助电路和第一晶体管的基极 - 发射极结之间的热连通允许热关断电路在温度超过关断温度时关闭辅助电路，并且热关断电路内置的热滞后可防止不期望的导通 - OFF辅助电路的振荡。

公开(公告)号：US5675276A

公开(公告)日：1997-10-07

申请号：US534634

申请日：1995-09-27

Applicant: Rakesh Goel

Inventor： Rakesh Goel

IPC: H03K3/2893 ,  H03K17/06 ,  H03K17/687 ,  H03K3/037

CPC classification number: H03K3/2893 ,  H03K17/063 ,  H03K17/6871

Abstract: A hysteresis circuit including first and second voltage reference circuits responsive to an input control signal for providing first and second voltage levels connected in series to produce a higher voltage level; a first switching circuit, responsive to the voltage reference circuits to turn on and provide an output drive signal when the higher voltage is reached; a second switching circuit, responsive to the first switching circuit turning on, for removing one of the first and second voltage levels to produce a lower voltage level; the first switching circuit turning off in response to the input level control signal decreasing below the lower voltage level.

Abstract translation: 一种滞后电路，包括响应于输入控制信号的第一和第二电压参考电路，用于提供串联连接的第一和第二电压电平以产生较高的电压电平; 第一开关电路，响应于所述电压参考电路导通并在达到较高电压时提供输出驱动信号; 第二开关电路，响应于所述第一开关电路导通，用于去除所述第一和第二电压电平中的一个以产生较低的电压电平; 第一开关电路响应于输入电平控制信号降低到较低电压电平以下而关断。

公开(公告)号：US4980581A

公开(公告)日：1990-12-25

申请号：US526267

申请日：1990-05-21

Applicant: Dwight D. Esgar ,  Ray D. Sundstrom

Inventor： Dwight D. Esgar ,  Ray D. Sundstrom

IPC: H03K19/0175 ,  H03K3/2893 ,  H03K5/24 ,  H03K19/086

CPC classification number: H03K3/2893 ,  H03K5/2418

Abstract: A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detection circuit responsive to the first and second inputs and having an output for providing a first predetermined voltage to the differential receiver circuit when the first and second inputs are in a normal mode and for providing an increased second predetermined voltage to the differential receiver circuit when the first and second inputs are in a tri-state mode wherein oscillation of the differential receiver circuit is prevented and the outputs are forced to known logic states while the noise margin of the differential receiver is increased without a sacrifice in common mode range.

Abstract translation: 具有第一和第二输入以及第一和第二输出的电路包括响应于第一和第二输入的差分接收器电路，用于在第一和第二输出处提供对应的输出逻辑信号。 一种三态检测电路，其响应于第一和第二输入，并且具有用于当第一和第二输入处于正常模式时向差分接收器电路提供第一预定电压的输出，并且用于向差分提供增加的第二预定电压 当第一和第二输入处于三态模式时，其中防止差分接收器电路的振荡，并且将输出强制为已知的逻辑状态，同时增加差分接收器的噪声容限而不牺牲共模范围 。

公开(公告)号：US4972103A

公开(公告)日：1990-11-20

申请号：US387454

申请日：1989-07-28

Applicant: Stephane Barbu

Inventor： Stephane Barbu

IPC: H03K3/2897 ,  H03K3/2893 ,  H03K5/08 ,  H03K17/30 ,  H03K17/60

CPC classification number: H03K3/2893

Abstract: An accelerated switching input circuit includes an emitter coupled logic stage having two transistors. The first transistor receives at its base an input signal and the second transistor receives at its base a control signal generated from the signal at the collector of the first transistor. A third transistor (T.sub.6) has its base connected to the collector of the first transistor (T.sub.3). A first resistor (R.sub.10), a second resistor (R.sub.11) and a third resistor (R.sub.12) are disposed in series between the emitter of the third transistor and a reference voltage (U.sub.REF) source. The point B common to the resistors R.sub.11 and R.sub.12 is coupled to the base of the second transistor (T.sub.4).

Abstract translation: 加速开关输入电路包括具有两个晶体管的发射极耦合逻辑级。 第一晶体管在其基极处接收输入信号，并且第二晶体管在其基极处接收从第一晶体管的集电极处的信号产生的控制信号。 第三晶体管（T6）的基极连接到第一晶体管（T3）的集电极。 第一电阻器（R10），第二电阻器（R11）和第三电阻器（R12）串联布置在第三晶体管的发射极和参考电压（UREF）源之间。 电阻器R11和R12共用的点B耦合到第二晶体管（T4）的基极。

公开(公告)号：US4694198A

公开(公告)日：1987-09-15

申请号：US890263

申请日：1986-07-29

Applicant: Yoshitaka Umeki

Inventor： Yoshitaka Umeki

IPC: H03K3/2893 ,  H03K3/2897 ,  H03K3/295

CPC classification number: H03K3/2893

Abstract: A Schmitt trigger circuit comprising input and output terminals, first and second voltage supply lines, a first transistor having its base connected to the input terminal and its the collector connected to the first voltage supply line though a load resistor, a second transistor having its collector connected to the first voltage supply line, a first constant-current source through which the first and second transistors have their respective emitters commonly connected to the second supply voltage line, and a third transistor having its collector connected to the first voltage supply line, its base connected to the first voltage supply line through the load resistor and to the collector of the first transistor and its emitter connected to the base of the second transistor. There is further provided a second constant-current source through which the third transistor has its base further connected to the second voltage supply line.

Abstract translation: 施密特触发电路包括输入和输出端子，第一和第二电压供应线路，第一晶体管的基极连接到输入端子，其集电极通过负载电阻器连接到第一电压供应线路，第二晶体管具有其集电极 连接到所述第一电压源线，第一恒流源，所述第一和第二晶体管通过所述第一恒流源具有共同连接到所述第二电源电压线的各自的发射极;以及第三晶体管，其集电极连接到所述第一电压供应线， 基极通过负载电阻连接到第一电压线，并连接到第一晶体管的集电极，其发射极连接到第二晶体管的基极。 还提供了第二恒流源，第三晶体管的基极通过第二恒流源进一步连接到第二电压源线。

公开(公告)号：US4525638A

公开(公告)日：1985-06-25

申请号：US571232

申请日：1984-01-16

Applicant: Randall C. Gray

Inventor： Randall C. Gray

IPC: H03K3/2893 ,  H03K17/30 ,  H03K5/153

CPC classification number: H03K3/2893 ,  H03K17/30

Abstract: In a zener referenced voltage threshold detector, the voltage at which a switching transistor turns on is determined by the breakdown voltage of a zener diode coupled between ground and the base of the switching transistor in conjunction with the base-emitter voltage of the switching transistor itself. In order to render the threshold detector circuit immune from noise at the trip point, a portion of the switching transistor's collector current is supplied to a second transistor which when turned on reduces the voltage at the base of the switching transistor.

Abstract translation: 在齐纳的参考电压阈值检测器中，开关晶体管导通的电压由耦合在开关晶体管的地和基极之间的齐纳二极管的结合开关晶体管本身的基极 - 发射极电压的击穿电压决定 。 为了使阈值检测器电路免于在跳变点处的噪声，开关晶体管的集电极电流的一部分被提供给第二晶体管，其在导通时降低开关晶体管的基极处的电压。

公开(公告)号：US4409497A

公开(公告)日：1983-10-11

申请号：US262498

申请日：1981-05-11

Applicant: Katsumi Nagano

Inventor： Katsumi Nagano

IPC: G01R19/165 ,  H03K3/2893 ,  H03K5/08 ,  H03K5/153 ,  H03K5/24

CPC classification number: G01R19/1659

Abstract: A window comparator circuit includes an input terminal, first and second reference voltage terminals to be supplied with first and second voltages different from each other, first and second comparators connected to one of the first and second reference voltage terminals and to the input terminal, and an output circuit connected to output terminals of the first and second comparators. The first comparator comprises first and second transistors whose bases are coupled to the first reference voltage terminal and input terminal and whose emitters are connected to each other, and a first constant current source for supplying a first current connected to commonly-connected emitters of the first and second transistors; the second comparator comprises third and fourth transistors whose bases are connected to the input terminal and second reference voltage terminal and whose emitters are connected to each other, and a second constant current source for supplying the first current connected to commonly-connected emitters of the third and fourth transistors; and the output circuit comprises a current mirror circuit to which is supplied with the sum of collector currents of the second and fourth transistors and to the output of which is connected to a third constant current source for supplying a second constant current which is a half of the first current, and an output transistor whose base is connected to an output terminal of the current mirror circuit.

Abstract translation: 窗口比较器电路包括：输入端子，要被提供彼此不同的第一和第二电压的第一和第二参考电压端子;连接到第一和第二参考电压端子之一和输入端子的第一和第二比较器，以及 连接到第一和第二比较器的输出端的输出电路。 第一比较器包括第一和第二晶体管，其基极耦合到第一参考电压端子和输入端子并且其发射极彼此连接;以及第一恒流源，用于提供连接到第一和第二参考电压端子的共同连接的发射极的第一电流 和第二晶体管; 第二比较器包括第三和第四晶体管，其基极连接到输入端子和第二参考电压端子并且其发射极彼此连接;以及第二恒流源，用于提供连接到第三电压源的共同连接的发射极的第一电流 和第四晶体管; 并且输出电路包括电流镜电路，其被提供有第二和第四晶体管的集电极电流之和，其输出端连接到第三恒流源，用于提供第二恒定电流，该第二恒定电流是 第一电流和输出晶体管，其基极连接到电流镜电路的输出端。

公开(公告)号：US4409495A

公开(公告)日：1983-10-11

申请号：US268643

申请日：1981-05-29

Applicant: Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

Inventor： Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

IPC: H03K3/2893 ,  H03K5/08 ,  H03K3/295

CPC classification number: H03K3/2893

Abstract: A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.

Abstract translation: 施密特触发电路具有降低噪声灵敏度和防止振荡的输入电压滞后特性。 在其输入级具有多发射极晶体管，并且在其输出级中具有第二晶体管。 多发射极晶体管包括第一发射极和第二发射极。 响应于施加到多发射极晶体管的基极的输入电压，第一发射极与开关操作相关联。 第二发射极与从第二晶体管的基极通过多发射极晶体管的基极到地的绘制电荷的操作相关联。 使用多发射极晶体管可防止输入电流随着输入电压的下降而大幅度增加。