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    High data rate interface with improved link synchronization
    11.
    发明申请
    High data rate interface with improved link synchronization 有权
    高数据速率接口，改善了链路同步

    公开(公告)号：US20050204057A1

    公开(公告)日：2005-09-15

    申请号：US11008024

    申请日：2004-12-08

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: G06F15/16 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04L29/06 ,  H04M1/725

    CPC classification number: H04L65/1069 ,  H04L12/40071 ,  H04L12/40117 ,  H04L29/06027 ,  H04L65/4069 ,  H04L65/80 ,  H04L69/18 ,  H04L69/22 ,  H04M1/72527 ,  H04W56/00 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    Digital data interface device
    13.
    发明授权
    Digital data interface device 有权
    数字数据接口设备

    公开(公告)号：US08873584B2

    公开(公告)日：2014-10-28

    申请号：US11285379

    申请日：2005-11-23

    Applicant: Behnam Katibian ,  George A Wiley ,  Brian Steele

    Inventor： Behnam Katibian ,  George A Wiley ,  Brian Steele

    IPC: H04J3/16 ,  H04M1/725

    CPC classification number: H04M1/7253

    Abstract: The present invention is directed a digital data interface device for transferring digital presentation data at a high rate over a communication link. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. In one example, a cellular telephone having a camera with an MDDI link and a digital data device interface is provided.

    Abstract translation: 本发明涉及一种用于通过通信链路以高速率传送数字呈现数据的数字数据接口设备。 数字数据接口设备包括消息解释器，内容模块和控制模块。 数字数据接口设备可以包括MDDI链路控制器。 数字数据接口设备可用于控制诸如照相机，条形码读取器，图像扫描器，音频设备或其他传感器的外围设备。 在一个示例中，提供具有具有MDDI链路的相机和数字数据设备接口的蜂窝电话。

    Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay
    14.
    发明授权
    Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay 失效
    基于表征的字线延迟和门延迟调整存储器阵列中的位线放电时间

    公开(公告)号：US08773927B2

    公开(公告)日：2014-07-08

    申请号：US13606342

    申请日：2012-09-07

    Applicant: Donald Albert Evans ,  Rasoju Veerabadra Chary ,  Richard John Stephani ,  Bijan Kumar Ghosh ,  Ronald Brian Steele

    Inventor： Donald Albert Evans ,  Rasoju Veerabadra Chary ,  Richard John Stephani ,  Bijan Kumar Ghosh ,  Ronald Brian Steele

    IPC: G11C7/00 ,  G11C7/22

    CPC classification number: G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/222 ,  G11C7/227 ,  G11C29/02 ,  G11C29/023 ,  G11C2029/1204

    Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

    Abstract translation: 存储器跟踪电路基于（i）在传播延迟之后在跟踪行的远端接收的信号和（ii）施加到基于晶体管的门延迟的信号来控制跟踪位线的放电持续时间。 跟踪电路（i）在（a）传播延迟和（b）基于晶体管的栅极延迟短于跟踪位线的不受控制的放电持续时间的一个或多个时延长放电持续时间，并且（ii） 否则不延长放电持续时间。 基于放电持续时间，跟踪电路激活复位信号，其复位时钟脉冲发生器以将存储器从访问操作切换到凹陷状态。 基于传播延迟和门延迟来控制放电持续时间以及因此复位信号允许时钟脉冲发生器调整存取时间以解决存储器阵列配置和处理，温度和电压条件。

    High data rate interface
    15.
    发明授权
    High data rate interface 有权
    高数据速率接口

    公开(公告)号：US08719334B2

    公开(公告)日：2014-05-06

    申请号：US10938354

    申请日：2004-09-10

    Applicant: Jon James Anderson ,  Brian Steele ,  George Alan Wiley ,  Shashank Shekhar

    Inventor： Jon James Anderson ,  Brian Steele ,  George Alan Wiley ,  Shashank Shekhar

    IPC: G06F15/16

    CPC classification number: H04L65/607 ,  H04L29/06027 ,  H04L69/14 ,  H04L69/18 ,  H04L69/22 ,  H04L69/24 ,  H04M1/72527 ,  Y02D50/30 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    High data rate interface with improved link synchronization
    16.
    发明授权
    High data rate interface with improved link synchronization 失效
    高数据速率接口，改善了链路同步

    公开(公告)号：US08687658B2

    公开(公告)日：2014-04-01

    申请号：US10997838

    申请日：2004-11-24

    Applicant: Jon James Anderson ,  Brian Steele ,  George Alan Wiley ,  Shashank Shekhar

    Inventor： Jon James Anderson ,  Brian Steele ,  George Alan Wiley ,  Shashank Shekhar

    IPC: H04J3/06

    CPC classification number: H04L67/42 ,  H04L29/06027 ,  H04L65/1069 ,  H04L65/4069 ,  H04L65/80 ,  H04L69/18 ,  H04L69/22 ,  H04M1/72527 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    Systems and methods for implementing cyclic redundancy checks
    17.
    发明授权
    Systems and methods for implementing cyclic redundancy checks 失效
    用于实现循环冗余校验的系统和方法

    公开(公告)号：US08667363B2

    公开(公告)日：2014-03-04

    申请号：US11285391

    申请日：2005-11-23

    Applicant: Brian Steele ,  George A. Wiley

    Inventor： Brian Steele ,  George A. Wiley

    IPC: H03M13/00

    CPC classification number: H04L1/0045 ,  H03M13/09 ,  H04L1/0061

    Abstract: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator, a CRC corrupter, an error detector and an error value generator. In one example, the digital transmission link is an MDDI link.

    Abstract translation: 本发明提供了用于实现循环冗余检查以改善链路初始化处理和交换系统错误信息的系统和方法。 在一个方面，提供了包括唯一模式检测器，CRC发生器，CRC初始化器和CRC校验器的循环冗余校验（CRC）校验器。 CRC校验器预先为CRC生成器提供了一个独特的模式。 在接收到通过数字传输链路接收的数据流中的唯一模式之后，CRC检查器继续检查CRC，而不需要排队和存储数据。 在另一方面，提供了一种CRC发生器系统，其有意地破坏CRC值以传输系统错误信息。 CRC发生器系统包括CRC发生器，CRC腐蚀器，误差检测器和误差值发生器。 在一个示例中，数字传输链路是MDDI链路。

    METHODS AND SYSTEMS FOR UPDATING A BUFFER
    20.
    发明申请
    METHODS AND SYSTEMS FOR UPDATING A BUFFER 有权
    更新缓冲区的方法和系统

    公开(公告)号：US20080129749A1

    公开(公告)日：2008-06-05

    申请号：US12020415

    申请日：2008-01-25

    Applicant: George Alan Wiley ,  Brian Steele

    Inventor： George Alan Wiley ,  Brian Steele

    IPC: G09G5/36

    CPC classification number: G09G5/393 ,  G09G5/12 ,  G09G5/395 ,  G09G2320/0247

    Abstract: The present invention relates to methods and systems for updating a buffer. In one aspect, the present invention provides a method for updating a buffer, which includes strategically writing to the buffer to enable concurrent read and write to the buffer. The method eliminates the need for double buffering, thereby resulting in implementation cost sad space saving's compared to conventional buffering approaches. The method also prevents image tearing when, used to update a frame buffer associated with a display, but is not limited to such applications. In another aspect, the present: invention provides efficient mechanisms to enable buffer update across a communication link. In one example, the present invention provides a method for relaying timing information across a communication link.

    Abstract translation: 本发明涉及用于更新缓冲器的方法和系统。 一方面，本发明提供了一种用于更新缓冲器的方法，其包括对缓冲器进行战略性地写入，以便能够对缓冲器进行并行读写。 该方法消除了对双缓冲的需要，从而与传统的缓冲方法相比，导致实现成本难以节省空间。 当用于更新与显示器相关联的帧缓冲器时，该方法还防止图像撕裂，但不限于此类应用。 在另一方面，本发明提供了有效的机制来实现跨越通信链路的缓冲器更新。 在一个示例中，本发明提供了一种用于在通信链路上中继定时信息的方法。

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