公开(公告)号：US20110013681A1

公开(公告)日：2011-01-20

申请号：US12836891

申请日：2010-07-15

Applicant: Qiuzhen Zou ,  George A. Wiley ,  Brian Steele

Inventor： Qiuzhen Zou ,  George A. Wiley ,  Brian Steele

IPC: H04B1/38

CPC classification number: H04L29/06 ,  G06F3/14 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2370/10 ,  G09G2370/16 ,  H04L47/10 ,  H04L47/283 ,  H04L47/41 ,  H04L69/324

Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

公开(公告)号：US5325396A

公开(公告)日：1994-06-28

申请号：US940662

申请日：1992-09-04

Applicant: David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson ,  George A. Wiley

Inventor： David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson ,  George A. Wiley

IPC: H04M1/00 ,  H03B28/00 ,  H03C3/00 ,  H03D3/00 ,  H04B1/40 ,  H04B3/00 ,  H04B7/00 ,  H04J3/02 ,  H04L25/03 ,  H04L27/00 ,  H04L27/18 ,  H04L27/20 ,  H04W84/16 ,  H03K3/80

CPC classification number: H03D3/007 ,  H04L27/00 ,  H04L27/2092 ,  H03B28/00 ,  H03C3/00 ,  H04L2025/03375 ,  H04L2025/03477

Abstract: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

Abstract translation: 用于与无线用户通信系统中的基站进行无线通信的用户单元包括FIR芯片，DIF（数字中频）芯片，单个处理器芯片和无线电装置。 处理器芯片对数字语音输入信号进行转码以提供数字输入符号; 解调从基站接收的输出信号以提供数字输出符号; 并从数字输出符号合成数字语音输出信号。 FIR芯片FIR对数字输入符号进行滤波，并产生用于对处理器芯片中的代码转换和合成操作进行定时的定时信号。 DIF芯片通过直接数字合成（DDS）数字合成数字中频信号，并用滤波后的输入符号对数字中频信号进行调制，以提供调制中频输入​​信号。 无线电进一步处理调制的输入信号以传输到基站。

公开(公告)号：US08730069B2

公开(公告)日：2014-05-20

申请号：US11937913

申请日：2007-11-09

Applicant: George A. Wiley ,  Brian Steele ,  Curtis D. Musfeldt

Inventor： George A. Wiley ,  Brian Steele ,  Curtis D. Musfeldt

IPC: H03M9/00

CPC classification number: H03M7/16

Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract translation: 提供双数据速率串行编码器。 串行编码器包括具有多个输入的多路复用器，耦合到多路复用器的输入的多个锁存器，使得锁存器能够更新其数据输入的启动器，以及用于选择多路复用器的多个输入之一的计数器 用于输出。 在另一方面，多路复用器在输入转换期间提供无毛刺输出。 多路复用器包括基于由计数器提供的输入选择序列的先验知识而优化的输出选择算法。

公开(公告)号：US08539119B2

公开(公告)日：2013-09-17

申请号：US11285389

申请日：2005-11-23

Applicant: Behnam Katibian ,  George A. Wiley

Inventor： Behnam Katibian ,  George A. Wiley

IPC: G06F3/00

CPC classification number: H04N21/43632 ,  H04M1/0214 ,  H04N21/41407 ,  H04N21/4223

Abstract: The present invention provides a digital data interface device message format that describes command and response messages to be exchanged between a digital device having a system controller and a digital data interface device. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used by a cellular telephone to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. The digital data interface device message format includes a transaction identification field, a count field, a command identification field and a status field. Optionally, the message format can include a data field. When an MDDI link is used, a digital data interface device message can be included in an MDDI register access packet.

Abstract translation: 本发明提供了一种数字数据接口设备消息格式，其描述了在具有系统控制器的数字设备和数字数据接口设备之间要交换的命令和响应消息。 数字数据接口设备包括消息解释器，内容模块和控制模块。 数字数据接口设备可以包括MDDI链路控制器。 数字数据接口设备可以被蜂窝电话用于控制诸如照相机，条形码读取器，图像扫描仪，音频设备或其他传感器的外围设备。 数字数据接口设备消息格式包括事务标识字段，计数字段，命令标识字段和状态字段。 可选地，消息格式可以包括数据字段。 当使用MDDI链路时，数字数据接口设备消息可以被包括在MDDI寄存器访问分组中。

公开(公告)号：US08472551B2

公开(公告)日：2013-06-25

申请号：US13301454

申请日：2011-11-21

Applicant: George A Wiley

Inventor： George A Wiley

IPC: H04L25/34 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

公开(公告)号：US20120008642A1

公开(公告)日：2012-01-12

申请号：US13240017

申请日：2011-09-22

Applicant: Behnam Katibian ,  George A. Wiley ,  Brian Steele

Inventor： Behnam Katibian ,  George A. Wiley ,  Brian Steele

IPC: G06F15/16

CPC classification number: H04L47/10 ,  H04L47/19 ,  H04L47/365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/44209 ,  H04N21/6377 ,  H04N21/658 ,  H04N21/6587

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract translation: 本发明提供了用于自适应数字数据传输速率控制的系统和方法。 用于通过传输链路自适应地传送分组的数字数据传输系统包括具有带宽控制模块的客户端设备和通过传输链路耦合到客户端设备的主机设备。 主机设备包括一个或多个带宽控制寄存器和数据包生成器。 带宽控制模块通过传输链路确定从主机设备向客户端设备发送的分组的分组速度和/或大小。 带宽控制寄存器存储所请求的分组大小和/或速率。 分组构建器在发送分组时访问这些寄存器以确定所请求的分组大小和/或速率。

公开(公告)号：US5008900A

公开(公告)日：1991-04-16

申请号：US394497

申请日：1989-08-14

Applicant: David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson ,  George A. Wiley

Inventor： David N. Critchlow ,  Moshe Yehushua ,  Graham M. Avis ,  Wade L. Heimbigner ,  Karle J. Johnson ,  George A. Wiley

IPC: H04M1/00 ,  H03B28/00 ,  H03C3/00 ,  H03D3/00 ,  H04B1/40 ,  H04B3/00 ,  H04B7/00 ,  H04J3/02 ,  H04L25/03 ,  H04L27/00 ,  H04L27/18 ,  H04L27/20 ,  H04W84/16

CPC classification number: H03D3/007 ,  H04L27/00 ,  H04L27/2092 ,  H03B28/00 ,  H03C3/00 ,  H04L2025/03375 ,  H04L2025/03477

Abstract: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

Abstract translation: 用于与无线用户通信系统中的基站进行无线通信的用户单元包括FIR芯片，DIF（数字中频）芯片，单个处理器芯片和无线电装置。 处理器芯片对数字语音输入信号进行转码以提供数字输入符号; 解调从基站接收的输出信号以提供数字输出符号; 并从数字输出符号合成数字语音输出信号。 FIR芯片FIR对数字输入符号进行滤波，并产生用于对处理器芯片中的代码转换和合成操作进行定时的定时信号。 DIF芯片通过直接数字合成（DDS）数字合成数字中频信号，并用滤波后的输入符号对数字中频信号进行调制，以提供调制中频输入​​信号。 无线电进一步处理调制的输入信号以传输到基站。

公开(公告)号：US08812706B1

公开(公告)日：2014-08-19

申请号：US10236657

申请日：2002-09-06

Applicant: Qiuzhen Zou ,  George A. Wiley ,  Brian Steele

Inventor： Qiuzhen Zou ,  George A. Wiley ,  Brian Steele

IPC: G06F13/00 ,  H04L29/06

CPC classification number: H04L29/06 ,  G06F3/14 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2370/10 ,  G09G2370/16 ,  H04L47/10 ,  H04L47/283 ,  H04L47/41 ,  H04L69/324

Abstract: A method, apparatus, and computer program product embodied on a hardware computer readable storage medium for compensating mismatched delays in at least two signals of a mobile display digital interface (MDDI) system. The method, apparatus, and computer program product embodied on a hardware computer readable storage medium sends a skew calibration packet from a host to a client. The host begins a calibration pattern; then toggling a data signal and a strobe signal at a substantially similar time which strobe signal is used by the client as a clock source. The method, apparatus, and computer program product embodied on a hardware computer readable storage medium also aligns a timing of the strobe signal and the data signal by providing varying delays and resetting the client to an original clock source before a next packet reception.

Abstract translation: 体现在硬件计算机可读存储介质上的方法，装置和计算机程序产品，用于补偿移动显示数字接口（MDDI）系统的至少两个信号中的不匹配的延迟。 实施在硬件计算机可读存储介质上的方法，装置和计算机程序产品从主机向客户端发送偏斜校准分组。 主机开始校准模式; 然后在基本相似的时间切换数据信号和选通信号，该选通信号被客户端用作时钟源。 实施在硬件计算机可读存储介质上的方法，装置和计算机程序产品还通过在下一个分组接收之前提供变化的延迟并将客户端重置为原始时钟源来对准选通信号和数据信号的定时。

公开(公告)号：US08699330B2

公开(公告)日：2014-04-15

申请号：US11285505

申请日：2005-11-23

Applicant: Behnam Katibian ,  George A. Wiley ,  Brian Steele

Inventor： Behnam Katibian ,  George A. Wiley ,  Brian Steele

IPC: H04J1/16

CPC classification number: H04L47/10 ,  H04L47/19 ,  H04L47/365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/44209 ,  H04N21/6377 ,  H04N21/658 ,  H04N21/6587

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract translation: 本发明提供了用于自适应数字数据传输速率控制的系统和方法。 用于通过传输链路自适应地传送分组的数字数据传输系统包括具有带宽控制模块的客户端设备和通过传输链路耦合到客户端设备的主机设备。 主机设备包括一个或多个带宽控制寄存器和数据包生成器。 带宽控制模块通过传输链路确定从主机设备向客户端设备发送的分组的分组速度和/或大小。 带宽控制寄存器存储所请求的分组大小和/或速率。 分组构建器在发送分组时访问这些寄存器以确定所请求的分组大小和/或速率。

公开(公告)号：US08064535B2

公开(公告)日：2011-11-22

申请号：US11712941

申请日：2007-03-02

Applicant: George A. Wiley

Inventor： George A. Wiley

IPC: H04L25/34 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract translation: 提供了高速串行接口。 一方面，高速串行接口使用三相调制来共同编码数据和时钟信息。 因此，消除了在接口的接收端处对偏斜电路的需要，从而减少了链路启动时间，并提高了链路效率和功耗。 在一个实施例中，高速串行接口使用比具有用于数据和时钟信息的单独导体的传统系统更少的信号导体。 在另一个实施例中，串行接口允许以任何速度发送数据，而没有接收端具有传输数据速率的先前知识。 另一方面，高速串行接口使用极性编码的三相调制来共同编码数据和时钟信息。 这进一步增加了串行接口的链路容量，允许在任何单个波特率间隔内传输多于一个位。