公开(公告)号：US6033965A

公开(公告)日：2000-03-07

申请号：US363074

申请日：1999-07-28

Applicant: Chen-Bin Lin ,  Feng-Ming Liu ,  James Ho ,  Yu-Ju Liu

Inventor： Chen-Bin Lin ,  Feng-Ming Liu ,  James Ho ,  Yu-Ju Liu

IPC: H01L27/06 ,  H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/0629

Abstract: A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.

Abstract translation: 一种在衬底上制造混合信号集成电路的工艺，其中衬底部分被场氧化物层覆盖。 在衬底的一部分上形成氧化物层，其中衬底的部分未被场氧化物层覆盖。 第一杂质被注入到基底中，其中第一杂质破坏氧化物层。 在氧化物层上形成缓冲层。 在缓冲层上形成多晶硅层。 将第二杂质注入到多晶硅层中，其中缓冲层防止氧化物层形式被第二杂质损坏。 蚀刻多晶硅层以除去多晶硅层，其中缓冲层防止氧化物层和衬底被蚀刻。 去除衬底上的缓冲层部分和损坏的氧化物层。 栅极氧化层形成在衬底上。

公开(公告)号：US06507059B2

公开(公告)日：2003-01-14

申请号：US09885467

申请日：2001-06-19

Applicant: Chong-Yao Chen ,  Chen-Bin Lin

Inventor： Chong-Yao Chen ,  Chen-Bin Lin

IPC: H01L31113

CPC classification number: H01L27/14689 ,  H01L27/14609

Abstract: A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.

Abstract translation: 一种制造CMOS图像传感器的方法。 在衬底上形成隔离层以将衬底分隔成光电二极管感测区域和晶体管元件区域。 接着，在晶体管元件区域上形成栅电极结构，然后在栅电极结构的两个侧面的晶体管元件区域形成源/漏区。 同时，在光电二极管感测区域上形成掺杂区域。 之后，在光电二极管感测区域上形成自对准势垒层，在衬底上形成保护层。 然后，在保护层上依次形成电介质层和金属导电线。 再次，在电介质层和金属导线上形成保护层，其中介电层和金属导线的数量取决于制造工艺。 在每个介电层之间形成保护层。

公开(公告)号：US06479317B2

公开(公告)日：2002-11-12

申请号：US09975618

申请日：2001-10-11

Applicant: Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

Inventor： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC: H01L2100

CPC classification number: H01L31/02162 ,  H01L27/14621 ,  H01L27/14636 ,  H01L29/665 ,  H01L31/02161

Abstract: The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises the following steps: A substrate is provided that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forming a composite layer on the substrate, wherein the composite layer at least also covers both the sensor area and the transistor area, and the composite layer increases the refractive index of light that propagates from the doped region into the composite layer; performing an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performing a salicide process to let top of the gate, the source and the drain are covered by a silicate. One main characteristic of the invention is that the composite layer can be used as an anti-reflection layer of the sensor area and a salicide block of the transistor region. The composite layer is made of several basic layers and refractive index of any basic layer is different from refractive indexes of adjacent basic layers.

Abstract translation: 本发明是一种用于整合抗反射层和自对准硅化物块的方法。 该方法包括以下步骤：提供被分成至少传感器区域和晶体管区域的衬底，其中传感器区域包括掺杂区域，并且晶体管区域包括晶体管，晶体管包括栅极，源极和漏极 ; 在所述基板上形成复合层，其中所述复合层至少还覆盖所述传感器区域和所述晶体管区域，并且所述复合层增加从所述掺杂区域传播到所述复合层中的光的折射率; 执行蚀刻工艺和光刻工艺以去除复合层的一部分，并使栅极顶部，源极和漏极不被复合层覆盖; 并且执行自对准处理以使浇口的顶部，源和漏被硅酸盐覆盖。 本发明的一个主要特征是复合层可以用作传感器区域的防反射层和晶体管区域的自对准硅化物块。 复合层由若干基本层构成，任何基层的折射率与相邻基层的折射率不同。

公开(公告)号：US06242315B1

公开(公告)日：2001-06-05

申请号：US09186126

申请日：1998-11-04

Applicant: Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

Inventor： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

IPC: H01L2120

CPC classification number: H01L28/55 ,  H01L21/76838 ,  H01L28/60

Abstract: A method of manufacturing the metallic electrodes of a capacitor in a mixed mode semiconductor device. The method comprises the steps of providing a substrate having a conductive layer and the lower electrode of a capacitor formed thereon, and then depositing a dielectric layer over the substrate. A first opening and a second opening are then formed in the dielectric layer. The first opening exposes a portion of the conductive layer while the second opening exposes a portion of the lower electrode. Finally, a conductive plug and the upper electrode of the capacitor are formed in the respective first and second openings that are in corresponding positions above the conductive layer and lower electrode, respectively.

Abstract translation: 一种在混合模式半导体器件中制造电容器的金属电极的方法。 该方法包括以下步骤：提供具有导电层和形成在其上的电容器的下电极的衬底，然后在衬底上沉积介电层。 然后在电介质层中形成第一开口和第二开口。 第一开口暴露导电层的一部分，而第二开口暴露下部电极的一部分。 最后，分别在导电层和下电极上方的相应位置的相应的第一和第二开口中形成导电插塞和电容器的上电极。

公开(公告)号：US6086951A

公开(公告)日：2000-07-11

申请号：US332342

申请日：1999-06-14

Applicant: Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

Inventor： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L28/55 ,  H01L28/60 ,  H01L21/76801 ,  H01L21/76838

Abstract: A method of forming metallic capacitor. The method includes forming a lower electrode for forming the capacitor and a metal conductive line over an inter-layer dielectric such that there are gaps between and on the sides of the lower electrode and the metal conductive line. Thereafter, a first oxide layer is formed that fills the gap, and then a second oxide layer is formed over the inter-layer dielectric. The second oxide layer is later patterned to form a cap oxide layer having an opening that exposes a portion of the lower electrode. Subsequently, a thin dielectric layer is formed over the lower electrode and the cap oxide layer. Finally, an upper electrode is formed over the thin dielectric layer filling the opening.

Abstract translation: 一种形成金属电容器的方法。 该方法包括形成用于形成电容器的下电极和在层间电介质上的金属导电线，使得在下电极和金属导线之间的两侧之间和之间存在间隙。 此后，形成填充间隙的第一氧化物层，然后在层间电介质上形成第二氧化物层。 随后将第二氧化物层图案化以形成具有暴露下部电极的一部分的开口的帽氧化物层。 随后，在下电极和盖氧化物层上形成薄介电层。 最后，在填充开口的薄介电层上形成上电极。