公开(公告)号：US06479317B2

公开(公告)日：2002-11-12

申请号：US09975618

申请日：2001-10-11

申请人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

发明人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC分类号： H01L2100

CPC分类号： H01L31/02162 ,  H01L27/14621 ,  H01L27/14636 ,  H01L29/665 ,  H01L31/02161

摘要： The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises the following steps: A substrate is provided that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forming a composite layer on the substrate, wherein the composite layer at least also covers both the sensor area and the transistor area, and the composite layer increases the refractive index of light that propagates from the doped region into the composite layer; performing an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performing a salicide process to let top of the gate, the source and the drain are covered by a silicate. One main characteristic of the invention is that the composite layer can be used as an anti-reflection layer of the sensor area and a salicide block of the transistor region. The composite layer is made of several basic layers and refractive index of any basic layer is different from refractive indexes of adjacent basic layers.

摘要翻译： 本发明是一种用于整合抗反射层和自对准硅化物块的方法。 该方法包括以下步骤：提供被分成至少传感器区域和晶体管区域的衬底，其中传感器区域包括掺杂区域，并且晶体管区域包括晶体管，晶体管包括栅极，源极和漏极 ; 在所述基板上形成复合层，其中所述复合层至少还覆盖所述传感器区域和所述晶体管区域，并且所述复合层增加从所述掺杂区域传播到所述复合层中的光的折射率; 执行蚀刻工艺和光刻工艺以去除复合层的一部分，并使栅极顶部，源极和漏极不被复合层覆盖; 并且执行自对准处理以使浇口的顶部，源和漏被硅酸盐覆盖。 本发明的一个主要特征是复合层可以用作传感器区域的防反射层和晶体管区域的自对准硅化物块。 复合层由若干基本层构成，任何基层的折射率与相邻基层的折射率不同。

公开(公告)号：US06541329B1

公开(公告)日：2003-04-01

申请号：US09682477

申请日：2001-09-07

申请人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

发明人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC分类号： H01L218234

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689

摘要： A plurality of active pixel sensors are formed on the surface of a semiconductor wafer. The semiconductor wafer comprises a P-type substrate, an active pixel sensor region and a periphery circuit region. A first active pixel sensor block mask (APSB mask) is formed to cover the active pixel sensor region, then at least one N-well on the surface of the semiconductor wafer not covered by the first APSB mask is formed. A second APSB mask and at least one N-well mask are formed to cover the active pixel sensor region and the region outside the P-well region. At least one P-well on the surface of the semiconductor wafer not covered by the second APSB mask and the N-well mask is formed. Finally, at least one photodiode and at least one complementary metal-oxide semiconductor (CMOS) transistor are formed on the surface of the active pixel sensor region.

摘要翻译： 在半导体晶片的表面上形成多个有源像素传感器。 半导体晶片包括P型衬底，有源像素传感器区域和外围电路区域。 形成第一有源像素传感器块掩模（APSB掩模）以覆盖有源像素传感器区域，然后形成未被第一APSB掩模覆盖的半导体晶片的表面上的至少一个N阱。 形成第二APSB掩模和至少一个N阱掩模以覆盖有源像素传感器区域和P阱区域外的区域。 形成未被第二APSB掩模和N阱掩模覆盖的半导体晶片的表面上的至少一个P阱。 最后，在有源像素传感器区域的表面上形成至少一个光电二极管和至少一个互补金属氧化物半导体（CMOS）晶体管。

公开(公告)号：US06906364B2

公开(公告)日：2005-06-14

申请号：US09892419

申请日：2001-06-26

申请人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

发明人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC分类号： H01L27/146 ,  H01L31/062 ,  H01L31/113 ,  H04N1/04

CPC分类号： H01L27/14643 ,  H01L27/14609

摘要： A structure of a CMOS image sensory device is described. A photodiode sensory region and a transistor device region are isolated from each other by an isolation layer formed in the substrate. A gate structure is located on the transistor device region, and a source/drain region is in the transistor device region beside the side of the gate structure. A doped region is in the photodiode sensory region. A self-aligned block is located on the photodiode sensory region and a protective layer is formed on the entire substrate.

摘要翻译： 描述CMOS图像感测装置的结构。 光电二极管感应区域和晶体管器件区域通过形成在衬底中的隔离层彼此隔离。 栅极结构位于晶体管器件区域上，源极/漏极区域位于栅极结构侧面旁边的晶体管器件区域中。 掺杂区域在光电二极管的感觉区域中。 自对准块位于光电二极管感应区上，在整个基板上形成保护层。

公开(公告)号：US06303406B1

公开(公告)日：2001-10-16

申请号：US09590722

申请日：2000-06-08

申请人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

发明人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC分类号： H01L2100

CPC分类号： H01L31/02162 ,  H01L27/14621 ,  H01L27/14636 ,  H01L29/665 ,  H01L31/02161

摘要： The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises following steps: provide a substrate that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forms a composite layer on the substrate, herein the composite layer at least also covers both sensor area and transistor area, and the composite layer increases refractive index of light that propagate from the doped region into the composite layer; performs an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performs a salicide process to let top of the gate, the source and the drain are covered by a silicate. One main characteristic of the invention is that the composite layer can be used as an anti-reflection layer of the sensor area and a salicide block of the transistor region. The composite layer is made of several basic layers and refractive index of any basic layer is different to refractive indexes of adjacent basic layers.

摘要翻译： 本发明是一种用于整合抗反射层和自对准硅化物块的方法。 该方法包括以下步骤：提供被分成至少传感器区域和晶体管区域的衬底，其中传感器区域包括掺杂区域，并且晶体管区域包括包括栅极，源极和漏极的晶体管; 在衬底上形成复合层，这里复合层至少还覆盖传感器面积和晶体管面积，并且复合层增加了从掺杂区域传播到复合层中的光的折射率; 进行蚀刻处理和光刻处理以去除复合层的一部分，并使栅极顶部，源极和漏极不被复合层覆盖; 并执行自对准处理以使顶部的栅极，源极和漏极被硅酸盐覆盖。 本发明的一个主要特征是复合层可以用作传感器区域的防反射层和晶体管区域的自对准硅化物块。 复合层由几层基本层组成，任何基层的折射率与相邻基层的折射率不同。

公开(公告)号：US06607951B2

公开(公告)日：2003-08-19

申请号：US09893140

申请日：2001-06-26

申请人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

发明人： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC分类号： H01L2100

CPC分类号： H01L27/14643 ,  H01L27/14687

摘要： A fabrication method for a CMOS image sensory device is described. An isolation layer is formed in the substrate to isolate a photodiode sensory region and a transistor device region. A gate structure is further formed on the transistor device region, followed by forming concurrently a source/drain region in the transistor device region beside the side of the gate structure and a doped region in the photodiode sensory region. Thereafter, a self-aligned block is formed on the photodiode sensory region, followed by forming a protective layer on the substrate.

公开(公告)号：US6033965A

公开(公告)日：2000-03-07

申请号：US363074

申请日：1999-07-28

申请人： Chen-Bin Lin ,  Feng-Ming Liu ,  James Ho ,  Yu-Ju Liu

发明人： Chen-Bin Lin ,  Feng-Ming Liu ,  James Ho ,  Yu-Ju Liu

IPC分类号： H01L27/06 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/0629

摘要： A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.

摘要翻译： 一种在衬底上制造混合信号集成电路的工艺，其中衬底部分被场氧化物层覆盖。 在衬底的一部分上形成氧化物层，其中衬底的部分未被场氧化物层覆盖。 第一杂质被注入到基底中，其中第一杂质破坏氧化物层。 在氧化物层上形成缓冲层。 在缓冲层上形成多晶硅层。 将第二杂质注入到多晶硅层中，其中缓冲层防止氧化物层形式被第二杂质损坏。 蚀刻多晶硅层以除去多晶硅层，其中缓冲层防止氧化物层和衬底被蚀刻。 去除衬底上的缓冲层部分和损坏的氧化物层。 栅极氧化层形成在衬底上。

公开(公告)号：US09184438B2

公开(公告)日：2015-11-10

申请号：US13123356

申请日：2009-10-02

申请人： Mino Green ,  Feng-Ming Liu

发明人： Mino Green ,  Feng-Ming Liu

IPC分类号： B44C1/22 ,  H01M4/134 ,  H01M4/04 ,  H01M4/36 ,  H01M4/66 ,  H01M10/052 ,  H01M4/131 ,  H01M4/02

CPC分类号： H01M4/134 ,  H01M4/049 ,  H01M4/131 ,  H01M4/362 ,  H01M4/661 ,  H01M10/052 ,  H01M2004/028 ,  Y02E60/122

摘要： A process for etching silicon to form silicon pillars on the etched surfaces, includes treating silicon with an etching solution that includes 5 to 10M HF 0.01 to 0.1M Ag+ ions and 0.02 to 0.2M NO3− ions. Further, NO3− ions in the form of alkali metal, nitric acid or ammonium nitrate salt is added to maintain the concentration of nitrate ions within the above range. The etched silicon is separated from the solution. The process provides pillars, especially for use as the active anode material in lithium ion batteries. The process is advantageous because it uses an etching bath containing only a small number of ingredients whose concentration needs to be controlled and it can be less expensive to operate than previous processes.

摘要翻译： 用于在蚀刻表面上蚀刻硅以形成硅柱的方法包括用蚀刻溶液处理硅，所述蚀刻溶液包括5至10M HF 0.01至0.1M Ag +离子和0.02至0.2M NO 3 - 离子。 此外，加入碱金属，硝酸或硝酸铵盐形式的NO 3 - 离子以将硝酸根离子的浓度维持在上述范围内。 蚀刻的硅与溶液分离。 该方法提供了支柱，特别用作锂离子电池中的活性阳极材料。 该方法是有利的，因为它使用仅含有少量成分的蚀刻液，其浓度需要被控制，并且可以比以前的方法操作更便宜。

公开(公告)号：US20140045062A1

公开(公告)日：2014-02-13

申请号：US14055371

申请日：2013-10-16

申请人： Mino Green ,  Feng-Ming Liu

发明人： Mino Green ,  Feng-Ming Liu

IPC分类号： H01M4/38 ,  H01M4/04

CPC分类号： H01M4/386 ,  C30B29/06 ,  C30B29/60 ,  C30B33/08 ,  H01M4/0402 ,  H01M4/131 ,  H01M4/133 ,  H01M4/134 ,  H01M4/1393 ,  H01M4/1395 ,  H01M4/5825 ,  H01M4/587 ,  H01M10/0525 ,  H01M2004/027 ,  Y02E60/122 ,  Y02P70/54 ,  Y10T29/49108 ,  Y10T29/49115

摘要： An electrically interconnected mass includes elongated structures. The elongated structures are electrochemically active and at least some of the elongated structures cross over each other to provide intersections and a porous structure. The elongated structures include doped silicon.

摘要翻译： 电连接的质量包括细长结构。 细长结构是电化学活性的，至少一些细长结构彼此交叉以提供交叉点和多孔结构。 细长结构包括掺杂硅。

公开(公告)号：US06834094B1

公开(公告)日：2004-12-21

申请号：US10736520

申请日：2003-12-17

申请人： Feng-Ming Liu ,  Cheng-Wei Chen

发明人： Feng-Ming Liu ,  Cheng-Wei Chen

IPC分类号： H03K2100

CPC分类号： H03K23/667

摘要： A multi-selection prescaler for dividing an input signal according to a ratio to obtain a desired frequency. The circuit has of a plurality of logic gates and D-flip-flops: a first frequency divider for receiving an input signal and generating a divided frequency; a second frequency divider connected to the first frequency divider for performing a further frequency division based on a selection switch having a plurality of selection signals and a plurality of AND gates; a module control for performing a logic operation on the selection signals and an external control signal (MC) by OR gates and being connected to the first frequency divider to control the divided frequency of the first frequency divider; and an output selection circuit connected to the second frequency divider for selecting output signal according to the selection signals.

摘要翻译： 一种用于根据比率划分输入信号以获得期望频率的多选预分频器。 电路具有多个逻辑门和D触发器：第一分频器，用于接收输入信号并产生分频; 连接到第一分频器的第二分频器，用于基于具有多个选择信号的选择开关和多个与门进行进一步的分频; 用于通过或门对所述选择信号执行逻辑运算的模块控制和外部控制信号（MC），并连接到所述第一分频器以控制所述第一分频器的分频; 以及连接到第二分频器的输出选择电路，用于根据选择信号选择输出信号。

公开(公告)号：US20150188122A1

公开(公告)日：2015-07-02

申请号：US14593674

申请日：2015-01-09

申请人： Mino Green ,  Feng-Ming Liu

发明人： Mino Green ,  Feng-Ming Liu

IPC分类号： H01M4/134 ,  H01M4/38

CPC分类号： H01M4/134 ,  H01M4/0492 ,  H01M4/1395 ,  H01M4/386 ,  H01M10/52 ,  H01M2004/027 ,  Y02E60/122 ,  Y02P70/54 ,  Y10T29/49108 ,  Y10T117/102 ,  Y10T428/2982

摘要： Pillared particles of silicon or silicon-comprising material and a method of fabricating the same are disclosed. These particles may be used to create both a composite anode structure with a polymer binder, a conductive additive and a metal foil current collector, and an electrode structure. The structure of the particles overcomes the problems of charge/discharge capacity loss.

摘要翻译： 披露了硅或含硅材料的柱状颗粒及其制造方法。 这些颗粒可用于产生具有聚合物粘合剂，导电添加剂和金属箔集电器的复合阳极结构和电极结构。 颗粒的结构克服了充放电容量损失的问题。