Abstract:
A device for controlling light source of an optical mouse by pulse width modulation includes an image sensor, a light source, a pulse width modulation generator, and a light-source controller. The image sensor is used for capturing an image. The light source provides illumination required for the image sensor to capture an image. The pulse width modulation generator generates a pulse-width modulated waveform. The light-source controller uses the pulse-width modulated waveform to illuminate the light source on and off alternatively.
Abstract:
A dome array device is disclosed, which includes a film plate, a plurality of metal flexible plates, and a covering layer. The film plate has a first surface and a second surface. A plurality of flexible press portions protrudes from the film plate. The metal flexible plates are respectively located on the second surface of the flexible press portions of the film plate. The covering layer is formed and covered on the first surface of the film plate. A plurality of plungers that respectively corresponds and locates on the flexible press portions protrudes from the covering layer. A plurality of function portions that is located around the flexible press portions extends and protrudes from the covering layer. Furthermore, a key structure with the dome array device is disclosed, and thereby the operation sensitivity is improved, the total thickness is reduced, and the manufacturing cost is decreased.
Abstract:
Disclosed is a nanofiber filter medium formed by electrospinning, having a low pressure drop and high filtration performance. The nanofiber layer thereof is constructed by at least two nanofibers, uniformly entangled with each other, with different fiber diameter distributions. Therefore, the nanofiber filter medium of the invention is completed. The described nanofiber filter medium has a low pressure drop and high filtration performance.
Abstract:
A convolutional interleaving and de-interleaving circuit and the method thereof are disclosed. The convolutional interleaving and de-interleaving circuit comprises an initial address generator, a first address generator, a second address generator, an address mixer, an adder, a controller and a memory. Wherein, the controller enables those address generators to provide or store corresponding channel addresses. Further, an adder is shared and memory addresses are appropriately arranged so as to reduce the requirement of registers. Accordingly, the required gate count and the chip layout area can be reduced.