公开(公告)号：US09153440B2

公开(公告)日：2015-10-06

申请号：US13428923

申请日：2012-03-23

Applicant: Chih-Han Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr-Jung Lin

Inventor： Chih-Han Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr-Jung Lin

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.

Abstract translation: 一种方法包括在衬底上提供第一掩模图案，形成与第一掩模图案的侧壁相邻的第一间隔物，去除第一掩模图案，形成邻接第一间隔物的侧壁的第二间隔物，在衬底上形成填充层， 并且在衬底上形成第二掩模图案。

公开(公告)号：US20100255654A1

公开(公告)日：2010-10-07

申请号：US12753972

申请日：2010-04-05

Applicant: Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jung Lin, JR. ,  Yu Chao Lin ,  Chih-Han Lin

Inventor： Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jung Lin, JR. ,  Yu Chao Lin ,  Chih-Han Lin

IPC: H01L21/762

CPC classification number: H01L21/76232

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.

Abstract translation: 本公开涉及集成电路制造，并且更具体地涉及具有几乎没有纹波的隔离结构的电子器件。 一种用于制造隔离结构的示例性方法，包括：在衬底的顶表面上形成衬垫氧化物层; 在所述衬垫氧化物层中形成开口，暴露所述衬底的一部分; 蚀刻衬底的暴露部分，在衬底中形成沟槽; 用绝缘体填充沟槽; 将衬垫氧化物层的表面和绝缘体的表面暴露于至少包含NH 3和含氟化合物的蒸汽混合物; 并在100℃至200℃的温度下加热基材。

公开(公告)号：US20080119040A1

公开(公告)日：2008-05-22

申请号：US11602344

申请日：2006-11-21

Applicant: Chih-Han Lin ,  Chien-Chung Chen ,  K.T. Lai ,  Hung-Lung Hu

Inventor： Chih-Han Lin ,  Chien-Chung Chen ,  K.T. Lai ,  Hung-Lung Hu

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L2221/1026

Abstract: A method for forming a dual damascene structure is provided. In one embodiment, a semiconductor substrate with a patterned protective layer formed thereover is provided. A conformal dielectric layer is formed over the protective layer. A patterned mask layer is formed over the dielectric layer. A portion of the dielectric layer is etched substantially up to about the top surface of the protective layer according to the pattern of the mask layer to form a trench. The protective layer is then removed to form a via hole. A conductive layer is formed in the via hole and the trench, thereby forming a dual damascene structure.

Abstract translation: 提供了一种形成双镶嵌结构的方法。 在一个实施例中，提供了其上形成有图案化保护层的半导体衬底。 在保护层上形成保形介电层。 在电介质层上形成图案化的掩模层。 根据掩模层的图案，电介质层的一部分基本上被蚀刻到保护层的顶表面以形成沟槽。 然后去除保护层以形成通孔。 在通孔和沟槽中形成导电层，由此形成双镶嵌结构。