公开(公告)号：US6064590A

公开(公告)日：2000-05-16

申请号：US130801

申请日：1998-08-07

Applicant: Chul-Hi Han ,  Sung-Hoi Hur

Inventor： Chul-Hi Han ,  Sung-Hoi Hur

IPC: H01L27/11 ,  G11C14/00 ,  G11C16/04

CPC classification number: G11C14/00

Abstract: A non-volatile static random access memory device configured by adding a floating gate type metal oxide semiconductor device to an SRAM including a pair of access elements respectively switched on and off in accordance with the state of a signal on an address line and adapted to establish a data transfer path between memory cell and associated negative and positive data lines, and a pair of inverters respectively coupled to the access elements, thereby allowing the SRAM to exhibit non-volatile memory characteristics. The floating gate type MOS device has a silicon substrate, a tunneling oxide film formed over the silicon substrate, a floating gate formed on the tunneling oxide film, an oxide film formed over the floating gate, a control gate formed over the oxide film, and a source and a drain respectively formed in an upper surface of the silicon substrate at both sides of the control gate. The source and drain of the floating gate type MOS device are electrically connected at the source and drain thereof to the input terminals of the inverters of the SRAM, respectively, so that it provides non-volatile memory characteristics to the SRAM by virtue of a difference in threshold voltage caused by charge stored in the floating gate thereof. This non-volatile SRAM device has a high density while exhibiting high-speed operation characteristics.

Abstract translation: 一种非易失性静态随机存取存储器件，通过根据地址线上的信号的状态将浮栅型金属氧化物半导体器件添加到包括分别接通和关断的一对存取元件的SRAM，并适于建立 存储器单元和相关联的负和正数据线之间的数据传输路径，以及分别耦合到访问元件的一对反相器，从而允许SRAM呈现非易失性存储器特性。 浮栅型MOS器件具有硅衬底，在硅衬底上形成的隧道氧化膜，在隧道氧化膜上形成的浮栅，形成在浮栅上的氧化膜，形成在氧化物膜上的控制栅，以及 分别形成在控制栅极两侧的硅衬底的上表面中的源极和漏极。 浮栅型MOS器件的源极和漏极分别在源极和漏极之间电连接到SRAM的反相器的输入端，使得其通过差异向SRAM提供非易失性存储器特性 在由其存储在其浮动栅极中的电荷引起的阈值电压中。 这种非易失性SRAM器件具有高密度，同时具有高速操作特性。

公开(公告)号：US5700699A

公开(公告)日：1997-12-23

申请号：US405501

申请日：1995-03-16

Applicant: Chul-Hi Han ,  Choong-Ki Kim ,  Jung-Yeal Lee ,  Kil-Hwan Oh

Inventor： Chul-Hi Han ,  Choong-Ki Kim ,  Jung-Yeal Lee ,  Kil-Hwan Oh

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/84

CPC classification number: H01L29/66757 ,  H01L21/28158 ,  H01L29/4908

Abstract: A method for fabricating the polycrystal silicon TFT under a low temperature which has an improved electron mobility, comprises the steps of forming an oxide film on a substrate, depositing a polycrystal silicon on the oxide film and patterning the polycrystal silicon so that source and drain regions and a channel region remain, growing a gate insulating layer on the patterned polycrystal silicon by ECR plasma thermal oxidation, depositing a material for a gate on the whole surface and removing the material and the gate insulating layer in portions except for a gate region to form the gate, and performing ion implantation on the exposed areas of the polycrystal silicon to form the source and drain regions.

Abstract translation: 在低温下制造具有改善的电子迁移率的多晶硅TFT的方法包括以下步骤：在衬底上形成氧化膜，在氧化物膜上沉积多晶硅并使多晶硅图形化，使得源极和漏极区域 并且保持沟道区域，通过ECR等离子体热氧化在图案化多晶硅上生长栅极绝缘层，在整个表面上沉积用于栅极的材料，并除去栅极区域以外的部分去除材料和栅极绝缘层以形成 并且在多晶硅的暴露区域上进行离子注入以形成源区和漏区。

公开(公告)号：US06033925A

公开(公告)日：2000-03-07

申请号：US864551

申请日：1997-05-27

Applicant: Chul-Hi Han ,  Hi-Deok Lee ,  Jae-Kwan Kim

Inventor： Chul-Hi Han ,  Hi-Deok Lee ,  Jae-Kwan Kim

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/2007 ,  H01L21/3063 ,  H01L21/76251 ,  Y10S438/977

Abstract: The present invention relates to a method for manufacturing a semiconductor wafer having a SOI wafer-like structure which is prepared on a silicon substrate by electrochemical etching, and an active-driven liquid crystal display employing the semiconductor wafer as a pixel switching wafer. In accordance with the method for manufacturing the SOI-type semiconductor wafer, a wafer having a good electrical insulation property, low leakage current and small parasitic capacity, like a SOI wafer, can be prepared, by employing a silicon substrate which is cheaper than the SOI substrate.

Abstract translation: 本发明涉及一种通过电化学蚀刻在硅衬底上制备具有SOI晶片状结构的半导体晶片的制造方法以及采用半导体晶片作为像素转换晶片的主动驱动液晶显示器。 根据SOI型半导体晶片的制造方法，可以通过采用比SOI晶片便宜的硅基板来制备具有良好的电绝缘性，低漏电流和小的寄生电容的晶片，如SOI晶片 SOI衬底。

公开(公告)号：US5810994A

公开(公告)日：1998-09-22

申请号：US725620

申请日：1996-10-03

Applicant: Ho Jun Lee ,  Choong Ki Kim ,  Chul Hi Han

Inventor： Ho Jun Lee ,  Choong Ki Kim ,  Chul Hi Han

IPC: B32B7/02 ,  C25F3/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/762 ,  H01L27/12

CPC classification number: C25F3/12 ,  H01L21/2007 ,  H01L21/76251

Abstract: A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.

Abstract translation: 绝缘体上硅器件晶片，具有均匀厚度的非常薄的单晶膜。 其通过通孔技术制造，其中在蚀刻装置中用基底硅蚀刻溶液蚀刻绝缘体上的单晶硅膜，通过以这样的方式施加通孔，使得该溶液可以用作阳极，并且SOI结构的衬底作为 一个阴极。 绝缘体的存在在单晶硅膜的下部区域和衬底中的电子产生空位，使得充满空位的下部区域不被基底硅蚀刻溶液除去，从而留下高度均匀的薄单晶硅 电影。