公开(公告)号：US6064590A

公开(公告)日：2000-05-16

申请号：US130801

申请日：1998-08-07

申请人： Chul-Hi Han ,  Sung-Hoi Hur

发明人： Chul-Hi Han ,  Sung-Hoi Hur

IPC分类号： H01L27/11 ,  G11C14/00 ,  G11C16/04

CPC分类号： G11C14/00

摘要： A non-volatile static random access memory device configured by adding a floating gate type metal oxide semiconductor device to an SRAM including a pair of access elements respectively switched on and off in accordance with the state of a signal on an address line and adapted to establish a data transfer path between memory cell and associated negative and positive data lines, and a pair of inverters respectively coupled to the access elements, thereby allowing the SRAM to exhibit non-volatile memory characteristics. The floating gate type MOS device has a silicon substrate, a tunneling oxide film formed over the silicon substrate, a floating gate formed on the tunneling oxide film, an oxide film formed over the floating gate, a control gate formed over the oxide film, and a source and a drain respectively formed in an upper surface of the silicon substrate at both sides of the control gate. The source and drain of the floating gate type MOS device are electrically connected at the source and drain thereof to the input terminals of the inverters of the SRAM, respectively, so that it provides non-volatile memory characteristics to the SRAM by virtue of a difference in threshold voltage caused by charge stored in the floating gate thereof. This non-volatile SRAM device has a high density while exhibiting high-speed operation characteristics.

摘要翻译： 一种非易失性静态随机存取存储器件，通过根据地址线上的信号的状态将浮栅型金属氧化物半导体器件添加到包括分别接通和关断的一对存取元件的SRAM，并适于建立 存储器单元和相关联的负和正数据线之间的数据传输路径，以及分别耦合到访问元件的一对反相器，从而允许SRAM呈现非易失性存储器特性。 浮栅型MOS器件具有硅衬底，在硅衬底上形成的隧道氧化膜，在隧道氧化膜上形成的浮栅，形成在浮栅上的氧化膜，形成在氧化物膜上的控制栅，以及 分别形成在控制栅极两侧的硅衬底的上表面中的源极和漏极。 浮栅型MOS器件的源极和漏极分别在源极和漏极之间电连接到SRAM的反相器的输入端，使得其通过差异向SRAM提供非易失性存储器特性 在由其存储在其浮动栅极中的电荷引起的阈值电压中。 这种非易失性SRAM器件具有高密度，同时具有高速操作特性。

公开(公告)号：US07608507B2

公开(公告)日：2009-10-27

申请号：US12216393

申请日：2008-07-03

申请人： Ji-Hwon Lee ,  Sung-Hoi Hur

发明人： Ji-Hwon Lee ,  Sung-Hoi Hur

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.

摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。 具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。 选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

公开(公告)号：US20050023600A1

公开(公告)日：2005-02-03

申请号：US10921656

申请日：2004-08-19

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

IPC分类号： H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76802 ,  H01L27/115 ,  H01L27/11524

摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

公开(公告)号：US06677639B2

公开(公告)日：2004-01-13

申请号：US10188389

申请日：2002-07-01

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

IPC分类号： H01L2976

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

公开(公告)号：US06677200B2

公开(公告)日：2004-01-13

申请号：US10194182

申请日：2002-07-12

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Sung-Hoi Hur

IPC分类号： H01L213366

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/66833 ,  Y10S438/954

摘要： A method of forming a non-volatile memory having a floating trap-type device is disclosed in the present invention. In the method, a relatively thick thermal oxide layer is formed at a semiconductor substrate and patterned to leave a thick thermal oxide pattern at a high-voltage region (a high-voltage region defining step). An oxide-nitride-oxide (ONO) layer is formed over substantially the entire surface (the substantial surface) of the semiconductor substrate and patterned to leave an ONO pattern at a cell memory region (a cell memory region defining step). After the high-voltage region defining step and the cell memory region defining step, a thermal oxidizing process is performed with respect to the semiconductor substrate where a low-voltage region is exposed, thereby forming a relatively thin gate insulation layer for a low-voltage type device (a low-voltage region defining region).

摘要翻译： 在本发明中公开了形成具有浮动陷阱型装置的非易失性存储器的方法。 在该方法中，在半导体衬底上形成相对较厚的热氧化物层，并将其图案化以在高电压区域（高电压区域限定步骤）处留下厚的热氧化物图案。 在半导体衬底的基本上整个表面（基本表面）上形成氧化物 - 氧化物（ONO）层，并将其图案化以在单元存储区（单元存储区定义步骤）处留下ONO图案。 在高电压区域定义步骤和电池存储区域限定步骤之后，对于暴露低电压区域的半导体衬底进行热氧化处理，从而形成用于低电压的较薄的栅极绝缘层 （低电压区域限定区域）。

公开(公告)号：US06461984B1

公开(公告)日：2002-10-08

申请号：US09535156

申请日：2000-03-24

申请人： Chui-Hi Han ,  Nae-In Lee ,  Sung-Hoi Hur ,  Jin-Woo Lee

发明人： Chui-Hi Han ,  Nae-In Lee ,  Sung-Hoi Hur ,  Jin-Woo Lee

IPC分类号： H01L2131

CPC分类号： H01L29/6675 ,  H01L21/28273 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/78609 ,  H01L29/7883

摘要： The present invention provides a highly reliable polycrystal silicon thin film transistor with N2O plasma oxide having an excellent leakage current characteristics comparable to the thermal oxide film formed on the crystalline silicon. Also, the present invention provides a method of fabricating EEPROM or flash memory using N2O plasma oxide as a tunnel oxide, and N2O plasma oxide film as an interpoly dielectric between the floating gate and the control gate.

摘要翻译： 本发明提供一种具有N2O等离子体氧化物的高度可靠的多晶硅薄膜晶体管，其具有与形成在结晶硅上的热氧化膜相当的优异的漏电流特性。另外，本发明提供一种使用N2O制造EEPROM或闪存的方法 等离子体氧化物作为隧道氧化物，N2O等离子体氧化膜作为浮置栅极和控制栅极之间的多晶硅电介质。

公开(公告)号：US07871921B2

公开(公告)日：2011-01-18

申请号：US11022240

申请日：2004-12-22

申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

公开(公告)号：US07538385B2

公开(公告)日：2009-05-26

申请号：US11790047

申请日：2007-04-23

申请人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Yoo-Cheol Shin ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954

摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

公开(公告)号：US07391071B2

公开(公告)日：2008-06-24

申请号：US11233857

申请日：2005-09-23

申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

公开(公告)号：US20080093677A1

公开(公告)日：2008-04-24

申请号：US11616947

申请日：2006-12-28

申请人： Tae Kyung Kim ,  Sung-Hoi Hur ,  Chang-Sub Lee ,  Seung-Chul Lee ,  Dong-Jun Lee

发明人： Tae Kyung Kim ,  Sung-Hoi Hur ,  Chang-Sub Lee ,  Seung-Chul Lee ,  Dong-Jun Lee

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L21/8238

CPC分类号： H01L27/0883 ,  H01L21/823412 ,  H01L29/1033 ,  H01L29/7833

摘要： Provided are semiconductor devices and methods of fabricating the same. A semiconductor device may include a semiconductor substrate with a device isolation layer defining HVE and HVD active regions. Gate insulation layer patterns may be disposed on the HVE and HVD active regions. Gate electrodes may be disposed on the gate insulation layer patterns to intersect the HVE and HVD active regions and the device isolation layer. An ion implantation layer may be disposed on the semiconductor substrate under the gate electrode of the HVD active region, spaced apart from the device isolation layer, and serves to adjust a threshold voltage.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括具有限定HVE和HVD有源区的器件隔离层的半导体衬底。 栅极绝缘层图案可以设置在HVE和HVD有源区上。 栅极电极可以设置在栅极绝缘层图案上以与HVE和HVD有源区域和器件隔离层相交。 离子注入层可以设置在与器件隔离层间隔开的HVD有源区的栅极下方的半导体衬底上，并用于调节阈值电压。