公开(公告)号：US06963499B2

公开(公告)日：2005-11-08

申请号：US10331135

申请日：2002-12-27

Applicant: Danilo Rimondi ,  Cosimo Torelli

Inventor： Danilo Rimondi ,  Cosimo Torelli

IPC: G11C7/20 ,  G11C11/419 ,  G11C7/00

CPC classification number: G11C7/20 ,  G11C11/419

Abstract: A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies, respectively. The cell also comprises means, responsive to a memory cell selection signal, for selectively connecting an input of at least one of the first and second inverter to at least one respective input/output data line, carrying an input datum to be written in the memory cell in a memory cell write operation and an output datum read from the memory cell in a memory cell read operation. For flash-clearing the memory cell, means are provided for switching at least one of the first and second voltage supply receiving means of at least one of the first and second inverters between the first voltage supply and the second voltage supply. The memory cell is particularly adapted to implement a flash-clear function in a memory device.

Abstract translation: 存储单元包括以锁存配置连接的第一和第二反相器。 逆变器具有分别用于接收第一和第二电压源的相应的第一和第二装置。 单元还包括响应于存储器单元选择信号的装置，用于将第一和第二反相器中的至少一个的输入选择性地连接到至少一个相应的输入/输出数据线，承载要写入存储器的输入数据 在存储单元读取操作中存储单元写入操作和从存储器单元读取的输出数据。 为了闪存存储单元，提供了用于在第一电压源和第二电压源之间切换第一和第二反相器中的至少一个的第一和第二电压供应接收装置中的至少一个的装置。 存储器单元特别适于在存储器件中实现闪光功能。

公开(公告)号：US06061286A

公开(公告)日：2000-05-09

申请号：US53720

申请日：1998-04-01

Applicant: Andrea Baroni ,  Danilo Rimondi ,  Michele Taliercio ,  Cosimo Torelli

Inventor： Andrea Baroni ,  Danilo Rimondi ,  Michele Taliercio ,  Cosimo Torelli

IPC: G11C11/41 ,  G11C7/14 ,  G11C11/413 ,  G11C11/419 ,  G11C7/00

CPC classification number: G11C7/14 ,  G11C11/419

Abstract: A memory device comprises an array of memory cells arranged in rows and columns, a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows, a dummy column of dummy memory cells substantially identical to the memory cells, precharge means for precharging the columns and the dummy column at a precharge potential when no row is selected, and programming means for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no row is selected, dummy column programming means for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state, and first detector means for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of the gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from the first logic state to the second logic state.

Abstract translation: 存储器件包括以行和列布置的存储器单元的阵列，用于将行解码器的相应选择输出发送到各行的多个门，与存储器单元基本相同的虚拟存储器单元的虚拟列，用于预充电的预充电装置 当没有行被选择时处于预充电电位的列和虚拟列，以及用于在各个编程电位设置所选择的列的编程装置。 该装置包括虚拟存储单元预设装置，用于当没有行被选择时，以第一逻辑状态预设虚拟存储单元;虚拟列编程装置，用于将虚拟列设置在与第一逻辑相反的第二逻辑状态的规定编程电位 状态和第一检测器装置，用于检测虚拟列已经从预充电电位放电到规定的编程电位，并因此使能所述多个门。 每个门具有耦合到相应的虚拟存储器单元的输入，使得一旦各个空存储器单元从第一逻辑状态切换到第二逻辑状态，门被禁止。

公开(公告)号：US5818775A

公开(公告)日：1998-10-06

申请号：US833901

申请日：1997-04-10

Applicant: Cosimo Torelli ,  Danilo Rimondi

Inventor： Cosimo Torelli ,  Danilo Rimondi

IPC: G11C8/08 ,  G11C11/418 ,  G11C13/00

CPC classification number: G11C8/08 ,  G11C11/418

Abstract: The invention relates to a memory comprising a matrix of memory cells; a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows of the matrix; a dummy bit line having an equivalent load as bit lines associated to columns of the matrix and which is discharged by a dummy memory cell when any row is selected; and circuitry for precharging the bit lines and the dummy bit line when no row is selected, and enabling said gates for transmission of the selection outputs of the row decoder in response to a clock signal. Each gate has an input coupled to the dummy bit line such that the gate is disabled as soon as the dummy bit line has discharged to a switching threshold of the gate.

Abstract translation: 本发明涉及包括存储器单元矩阵的存储器; 多个门，用于将行解码器的各个选择输出发送到矩阵的各行; 虚拟位线具有作为与矩阵的列相关联的位线的等效负载，并且当选择任何行时由虚拟存储器单元放电; 以及用于当没有行被选择时对位线和虚拟位线进行预充电的电路，以及响应于时钟信号使所述门用于传送行解码器的选择输出。 每个门具有耦合到虚拟位线的输入，使得一旦虚拟位线已经放电到门的切换阈值，门被禁止。