公开(公告)号：US5440715A

公开(公告)日：1995-08-08

申请号：US44543

申请日：1993-04-06

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F17/30 ,  G11C15/00 ,  G06F12/00

CPC分类号： G06F17/30982 ,  G11C15/00

摘要： Apparatus and a method for easily expanding the effective width of the data words of a CAM without significantly increasing the basic width of the data storage registers or comparand register. A plurality of comparison blocks each include a register for data words having a predetermined width. Each data word includes a start bit, which indicates that a data word is the first data word of a much larger data word (or data line), and a chain bit, which indicates that a match has occurred between part of a comparand and the data word stored in the register. A maskable comparator provides a match output signal. The start bit is initially loaded into the chain-bit register for a data word. A latch is provided for storing the value of the chain bit from a preceding register into the chain-bit register of a following register. A priority encoder receives the match output signals from each of the comparators of the comparison blocks to identify the highest-priority comparison block, and the corresponding data line.

摘要翻译： 用于容易地扩展CAM的数据字的有效宽度的装置和方法，而不显着增加数据存储寄存器或比较寄存器的基本宽度。 多个比较块各自包括具有预定宽度的数据字的寄存器。 每个数据字包括起始位，其表示数据字是大得多的数据字（或数据线）的第一个数据字，以及指示匹配在比较器的一部分和 数据字存储在寄存器中。 可屏蔽比较器提供匹配输出信号。 起始位最初被加载到数据字的链 - 位寄存器中。 提供锁存器，用于将来自前一个寄存器的链码的值存储到后续寄存器的链 - 位寄存器中。 优先编码器从比较块的每个比较器接收匹配输出信号，以识别最高优先级比较块和对应的数据线。

公开(公告)号：US5255185A

公开(公告)日：1993-10-19

申请号：US724793

申请日：1991-07-02

申请人： David L. Mowers ,  Santo A. Lamantia ,  David J. Mueller ,  Bruce N. Alleshouse ,  Victor S. Barczyk ,  Gerald A. Pierce ,  David C. Wyland ,  Lawrence E. Demar ,  Paul G. Dussault

发明人： David L. Mowers ,  Santo A. Lamantia ,  David J. Mueller ,  Bruce N. Alleshouse ,  Victor S. Barczyk ,  Gerald A. Pierce ,  David C. Wyland ,  Lawrence E. Demar ,  Paul G. Dussault

IPC分类号： A63D1/00 ,  A63D5/04 ,  A63D5/08 ,  G06F3/14 ,  G06F19/00 ,  G06F15/44

CPC分类号： G06F3/1423 ,  A63D1/00 ,  A63D5/04 ,  A63D5/08 ,  A63D2005/042 ,  G09G2360/04

摘要： A bowling center system includes a plurality of lane pair control systems each including a pin setting device for each lane, a pin setter control unit, a game scoring control unit, a bowler input station and a pair of overhead display monitors. A manager's control system provides accounting control over the bowling center system and is operable to communicate with a selected game control unit as necessary. A plurality of remote terminals are provided associated with selected ones of the lane pair control systems. Each remote terminal system includes a keyboard and a display monitor. The remote terminal operates under the control of the game unit to allow a user thereof to enter requests for video displays. The video displays include, the example, ball trajectory displays which illustrate the path of the ball in the bowling lane, or dynamic displays, such as for training, generated by video source devices associated with the manager's control system.

摘要翻译： 保龄球中心系统包括多个车道对控制系统，每个车道对控制系统包括用于每个车道的销钉设置装置，销钉设定器控制单元，游戏评分控制单元，礼帽输入站和一对架空显示监视器。 经理的控制系统提供对保龄球中心系统的会计控制，并且可操作地根据需要与选定的游戏控制单元进行通信。 多个远程终端提供与选定的一对通道对控制系统相关联。 每个远程终端系统包括键盘和显示监视器。 远程终端在游戏单元的控制下操作，以允许其用户输入视频显示请求。 视频显示器包括示例，示出保龄球道中球的路径的球轨迹显示器，或者与管理者的控制系统相关联的视频源设备产生的用于训练的动态显示。

公开(公告)号：US4882709A

公开(公告)日：1989-11-21

申请号：US236552

申请日：1988-08-25

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407

CPC分类号： G11C7/109 ,  G11C7/00 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00

摘要： To provide a means for the safe, premature, abortion of a write cycle without additional, read cycle, pipeline delays multiplexers and registers are included configured to store the address and data signals externally developed during a write cycle and to store in a RAM array the stored data at the stored address during the next write cycle. A comparator is included, configured to compare each stored address with each current address. Also included is a multiplexer configured to, during a read cycle, provide from the RAM array the currently addressed data when the current address is different than the stored address and to, during a read cycle, provide the register stored data when the current address matches the stored address.

公开(公告)号：US4307379A

公开(公告)日：1981-12-22

申请号：US67660

申请日：1979-08-20

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F9/22 ,  H05K1/00 ,  H04Q3/00

CPC分类号： G06F9/223 ,  H05K1/0286

摘要： An integrated circuit component having an array of rows and columns of programmable coupling elements, the rows being coupled to a plurality of independent input signals and the columns being coupled to output ports through a plurality of selectors. With such circuit component the independent input signals may be selectively coupled to the output ports in accordance with the programmed state of the programmable coupling elements and in accordance with control signals fed to the selectors. Therefore, if it is desired to change the coupling of the input signals to the output ports for the given control signal a different circuit component having differently programmed coupling elements may replace the previously programmed circuit component without requiring changes to printed circuit board connectors.

摘要翻译： 具有可编程耦合元件的行和列的阵列的集成电路组件，所述行耦合到多个独立的输入信号，并且所述列通过多个选择器耦合到输出端口。 利用这样的电路部件，独立输入信号可以根据可编程耦合元件的编程状态并且根据馈送到选择器的控制信号选择性地耦合到输出端口。 因此，如果希望将输入信号与给定控制信号的输出端口的耦合改变，则具有不同编程的耦合元件的不同电路部件可替代先前编程的电路部件，而不需要改变印刷电路板连接器。

公开(公告)号：US06738837B1

公开(公告)日：2004-05-18

申请号：US10062111

申请日：2002-02-01

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F1328

CPC分类号： G06F13/28

摘要： A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.

摘要翻译： 具有拆分事务存储器访问的数字系统。 数字系统可以通过位于数字系统的处理器和系统总线之间的读缓冲器（FIFO）从系统存储器访问数据。 读缓冲器由两个FIFO（用于读取数据的第一输入数据FIFO）和用于发送读请求的第二输出地址FIFO实现。 数据系统的处理器可以访问数据FIFO并读取数据，同时数据传输仍在进行中。 这会降低处理延迟，从而使处理器可以自由执行其他任务。

公开(公告)号：US06708259B1

公开(公告)日：2004-03-16

申请号：US10061543

申请日：2002-02-01

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F1200

CPC分类号： G06F13/1668

摘要： Methods for waking up an idle memory transfer controller (MTC) in response to an event from an external source. The first mechanism, Parameter List Pointer (PLP) FIFO Wake Up, wakes up an MTC after an external agent writes to an MTC's PLP FIFO. This activates the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This mechanism allows the MTC to distinguish between multiple possible originators of multiple possible wake-up events; wake-up events may be queued. Events may be directed to particular MTCs or to the next MTC available to process the event. The second mechanism wakes up an MTC after an external agent writes to an MTC's external wake-up address. This sets the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This approach only recognizes one event and one source. Events may not be queued using this approach.

摘要翻译： 响应于来自外部源的事件唤醒空闲存储器传输控制器（MTC）的方法。 参数列表指针（PLP）FIFO唤醒的第一个机制在外部代理向MTC的PLP FIFO写入之后唤醒MTC。 这将激活MTC的运行位，使MTC能够由存储器传输引擎仲裁器选择执行指令。 这种机制允许MTC区分多个可能的唤醒事件的多个可能的发起者; 唤醒事件可能排队。 可以将事件定向到可用于处理事件的特定MTC或下一个MTC。 外部代理程序写入MTC的外部唤醒地址后，第二种机制唤醒MTC。 这将设置MTC的运行位，使得MTC可以由内存传输引擎仲裁器选择执行指令。 这种方法只能识别一个事件和一个源。 事件可能不会使用这种方法排队。

公开(公告)号：US06215350B1

公开(公告)日：2001-04-10

申请号：US08959958

申请日：1997-10-24

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： H03K17687

CPC分类号： H03K17/693 ,  H03K17/04106 ,  H03K17/04113

摘要： A fast switching, device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

摘要翻译： 用于在两个输入/输出端口之间传递或阻塞信号的快速切换装置包括具有第一和第二端子和控制端子的晶体管。 第一和第二端子连接在两个端口之间。 当晶体管导通时，晶体管在端口之间传递信号，并且在晶体管截止时阻止端口之间的信号通过。 当晶体管导通时，第一和第二端子之间的电阻小于约10欧姆。 该装置还包括用于控制晶体管的控制端以使其接通或断开的驱动器。 优选地，第一或第二端子与参考电位之间的电容小于约50pF。

公开(公告)号：US06205462B1

公开(公告)日：2001-03-20

申请号：US09414322

申请日：1999-10-06

申请人： David C. Wyland ,  David A. Harrison

发明人： David C. Wyland ,  David A. Harrison

IPC分类号： G06F744

CPC分类号： G06F7/5443 ,  G06F2207/3824

摘要： Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in a special combined data format which prescribes a mantissa and an exponent for both integer and floating point operands. The exponent adder circuit adds the exponents of the two operands. But if before the addition the exponent adder circuit detects an integer as an operand, it replaces the exponent of the integer by a substitute value in that addition. This substitute value is related to the number of bits of the mantissa of the integer. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sum of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.

摘要翻译： 公开了一种乘法累加电路，其包括指数加法器电路，尾数乘法器电路，移位器，全加器和累加器。 产品加法器电路以特殊的组合数据格式接收两个操作数，它们规定了整数和浮点操作数的尾数和指数。 指数加法器电路将两个操作数的指数相加。 但是如果在加法之前，指数加法器电路检测一个整数作为一个操作数，它将以该加法代替整数的指数。 该替代值与整数的尾数的位数有关。 尾数乘法器电路将两个操作数的两个奇数相乘。 移位器根据由指数加法器电路产生的加法结果之和将乘积乘积的乘积移位到预定义的固定点格式。 全加器将此移位乘积加到累加器的当前内容。

公开(公告)号：US09755636B2

公开(公告)日：2017-09-05

申请号：US14747886

申请日：2015-06-23

申请人： David C. Wyland ,  Jonathan Alan Dutra

发明人： David C. Wyland ,  Jonathan Alan Dutra

IPC分类号： H03K17/687 ,  H03K17/567 ,  H03K17/0412 ,  H03K5/1534

CPC分类号： H03K17/567 ,  H03K5/1534 ,  H03K17/04123 ,  H03K17/6877

摘要： A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided. The inductive circuit is coupled to the gate of the switching device and further coupled to receive the charging voltage such that application of the charging voltage to the inductive circuit is with a polarity that induces a first current to flow through the inductor in a direction corresponding to charge moving away from the gate and such that discontinuation of the application of the charging voltage to the inductive circuit induces a second current flowing through the inductor in the direction corresponding to charge moving away from the gate such that the second current discharges the gate of the switching device. Faster turn off of the switching device is thus made possible and is synchronized to the discontinuation of the charging voltage.

公开(公告)号：US06810455B2

公开(公告)日：2004-10-26

申请号：US09968097

申请日：2001-09-28

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F13362

CPC分类号： G06F13/364

摘要： Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies. If a potential bus master is chosen to be the winning bus master, the centralized bus arbiter activates the winning bus master's dedicated bus grant line for the same number of bus clock cycles as requested by the bus master, i.e. for three bus clock cycles. So, the bus master will have sufficient use of the bus for its desired operation. After that, the arbiter chooses the next winning bus master and activates its dedicated grant line in the same manner described above, and so on.

摘要翻译： 公开了一种总线仲裁系统和方法，其假设使用总线的每个操作需要从一到五个总线时钟周期。 每个潜在总线主机具有专用总线请求线和专用总线授权线，两者均连接到本发明的总线仲裁系统中的集中式总线仲裁器。 当一个潜在的总线主机想要使用总线，例如三个总线时钟周期时，总线主机激活其专用总线请求线，使其总线使用时间相同数量的总线时钟周期（即三个总线时钟周期 ）。 这三个时钟宽的总线请求脉冲被记录在集中式总线仲裁器的总线请求记录电路中。 根据任何总线仲裁政策，可以通过集中式总线仲裁器向获胜的总线主机授予访问总线。 如果选择一个潜在的总线主机作为获胜总线主控器，则集中式总线仲裁器根据总线主机的要求（即三个总线时钟周期），激活获胜总线主控专用总线授权线，使其达到相同数量的总线时钟周期。 因此，总线主人将充分利用公共汽车进行所需的操作。 之后，仲裁者选择下一个获胜的总线主机，并以与上述相同的方式激活其专用授权线，等等。