公开(公告)号：US08060725B2

公开(公告)日：2011-11-15

申请号：US11768481

申请日：2007-06-26

Applicant: Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

Inventor： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

IPC: G06F15/00

CPC classification number: G06F9/3012 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891

Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.

Abstract translation: 用于多媒体应用的处理器架构包括提供矢量数据处理能力的处理器集群。 处理器集群中的处理元件根据单指令多数据（SIMD）功能处理位长度为N的数据和位长度为N / 2，N / 4等的数据。 负载单元根据相同的指令加载到要处理的处理器集群数据中。 集群间数据路径在处理器集群之间交换数据。 集群间数据路径是可扩展的，以激活所选择的处理器集群。 处理器在SIMD，标量和矢量数据上同时运行。

公开(公告)号：US20110060975A1

公开(公告)日：2011-03-10

申请号：US12850056

申请日：2010-08-04

Applicant: Francesco PAPPALARDO ,  Giuseppe Notarangelo ,  Elio Guidetti

Inventor： Francesco PAPPALARDO ,  Giuseppe Notarangelo ,  Elio Guidetti

IPC: G06F11/00

CPC classification number: G06F11/0751 ,  G06F11/1608 ,  G06F11/1629 ,  H03K19/007

Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.

Abstract translation: 通过以时钟信号计时的数字电子电路中的噪声脉冲引起的误差是通过在给定的时间间隔内为时钟信号提供至少一个额外的时钟信号偏移来检测的，并且对电路的至少一个分量执行比较 两个版本之间的对应关系和相同的信号。 比较由附加时钟信号计时，并且所述信号的两个版本之间不存在对应关系，通过噪声脉冲识别电路中感应的误差。

公开(公告)号：US07372916B2

公开(公告)日：2008-05-13

申请号：US10670993

申请日：2003-09-25

Applicant: Francesco Pappalardo ,  Giuseppe Notarangelo

Inventor： Francesco Pappalardo ,  Giuseppe Notarangelo

IPC: H04L27/00

CPC classification number: G06F13/4072 ,  G06F13/4213

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract translation: 数字信号在给定时刻的总线上以非编码格式和编码格式有选择地发送。 基于在上述给定时刻的总线上发送的信号与总线上的信号发送器的比较，部分地采用以非编码格式或编码格式发送信号的决定 在前一时刻，以便最小化总线上的开关活动。

公开(公告)号：US20050283587A1

公开(公告)日：2005-12-22

申请号：US11145780

申请日：2005-06-06

Applicant: Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso

Inventor： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso

IPC: G06F1/32 ,  G06F15/00 ,  G06F15/80

CPC classification number: G06F15/8023 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3885 ,  G06F9/3887 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.

Abstract translation: 处理器架构包括用于处理输入信号的多个处理元件。 该架构根据包括行和列的矩阵来组织，其列包括至少一个具有计算部分的微处理器块和能够接收相同输入信号的一组相关联的处理元件。 相关联的处理元件的数量在列的方向上选择性地变化，以便利用所述信号的并行性。 该架构可以在要执行的算法的最佳配置中以各种尺寸缩放。

公开(公告)号：US20050281562A1

公开(公告)日：2005-12-22

申请号：US10963737

申请日：2004-10-12

Applicant: Francesco Pappalardo ,  Giuseppe Notarangelo ,  Giuseppe Visalli

Inventor： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Giuseppe Visalli

IPC: H04B10/50 ,  H04B10/516 ,  H04B10/80 ,  H04L25/49 ,  H04B10/04

CPC classification number: H04B10/5055 ,  H04B10/503 ,  H04B10/516 ,  H04B10/801 ,  H04L25/4915

Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.

Abstract translation: 一种用于在光学连接上传送具有第一和第二逻辑状态的输入数据序列的方法，包括在光学连接上传输之前对输入数据序列进行编码，其中编码使编码数据序列中的第一逻辑状态最小化。 编码包括：在多条总线上并行布置输入数据序列; 对输入数据序列中的第一逻辑状态进行计数; 将计数结果与等于一半行的值进行比较; 并且如果计数结果大于输入数据序列的行的一半，则对行上的输入数据序列进行逻辑反相。 该方法还包括：排序输入数据序列的值; 识别具有第一逻辑状态的第一值; 以及将所述编码操作恰好应用于具有所述第一逻辑状态的所述第一值之后的有序值。