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1.发明授权Method for transmitting a data flow over an optical bus, corresponding system and computer program product 有权用于通过光学总线，对应的系统和计算机程序产品传输数据流的方法公开(公告)号：US07352301B2
公开(公告)日：2008-04-01
申请号：US10963737
申请日：2004-10-12
IPC分类号： H03M5/00
CPC分类号： H04B10/5055 , H04B10/503 , H04B10/516 , H04B10/801 , H04L25/4915
摘要： A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.
摘要翻译： 一种用于在光学连接上传送具有第一和第二逻辑状态的输入数据序列的方法，包括在光学连接上传输之前对输入数据序列进行编码，其中编码使编码数据序列中的第一逻辑状态最小化。 编码包括：在多条总线上并行布置输入数据序列; 对输入数据序列中的第一逻辑状态进行计数; 将计数结果与等于一半行的值进行比较; 并且如果计数结果大于输入数据序列的行的一半，则对行上的输入数据序列进行逻辑反相。 该方法还包括：排序输入数据序列的值; 识别具有第一逻辑状态的第一值; 以及将所述编码操作恰好应用于具有所述第一逻辑状态的所述第一值之后的有序值。
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2.发明申请Method for transmitting a data flow over an optical bus, corresponding system and computer program product 有权用于通过光学总线，对应的系统和计算机程序产品传输数据流的方法公开(公告)号：US20050281562A1
公开(公告)日：2005-12-22
申请号：US10963737
申请日：2004-10-12
IPC分类号： H04B10/50 , H04B10/516 , H04B10/80 , H04L25/49 , H04B10/04
CPC分类号： H04B10/5055 , H04B10/503 , H04B10/516 , H04B10/801 , H04L25/4915
摘要： A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.
摘要翻译： 一种用于在光学连接上传送具有第一和第二逻辑状态的输入数据序列的方法，包括在光学连接上传输之前对输入数据序列进行编码，其中编码使编码数据序列中的第一逻辑状态最小化。 编码包括：在多条总线上并行布置输入数据序列; 对输入数据序列中的第一逻辑状态进行计数; 将计数结果与等于一半行的值进行比较; 并且如果计数结果大于输入数据序列的行的一半，则对行上的输入数据序列进行逻辑反相。 该方法还包括：排序输入数据序列的值; 识别具有第一逻辑状态的第一值; 以及将所述编码操作恰好应用于具有所述第一逻辑状态的所述第一值之后的有序值。
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公开(公告)号：US09378077B2
公开(公告)日：2016-06-28
申请号：US12850056
申请日：2010-08-04
IPC分类号： G06F11/00 , G06F11/07 , G06F11/16 , H03K19/007
CPC分类号： G06F11/0751 , G06F11/1608 , G06F11/1629 , H03K19/007
摘要： Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.
摘要翻译： 通过以时钟信号计时的数字电子电路中的噪声脉冲引起的误差是通过在给定的时间间隔内为时钟信号提供至少一个额外的时钟信号偏移来检测的，并且对电路的至少一个分量执行比较 两个版本之间的对应关系和相同的信号。 比较由附加时钟信号计时，并且所述信号的两个版本之间不存在对应关系，通过噪声脉冲识别电路中感应的误差。
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4.发明申请METHOD AND ARRANGEMENT FOR CACHE MEMORY MANAGEMENT, RELATED PROCESSOR ARCHITECTURE 有权缓存记忆管理的方法与布置，相关处理器架构公开(公告)号：US20080016317A1
公开(公告)日：2008-01-17
申请号：US11768462
申请日：2007-06-26
IPC分类号： G06F15/00
CPC分类号： G06F12/084 , G06F12/0886 , Y02D10/13
摘要： A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.
摘要翻译： 耦合到包括处理器集群的处理器的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供用于存储用于处理的数据的数据位置同时操作标量和矢量数据。 数据位置以标量模式或矢量模式进行访问。 这通过明确地映射标量的数据位置和矢量的数据位置来完成。
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公开(公告)号：US07831804B2
公开(公告)日：2010-11-09
申请号：US12130861
申请日：2008-05-30
IPC分类号： G06F15/80
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F15/8023 , Y02D10/171
摘要： A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.
摘要翻译： 处理器架构包括用于处理输入信号的多个处理元件。 该架构根据包括行和列的矩阵来组织，其列包括至少一个具有计算部分的微处理器块和能够接收相同输入信号的一组相关联的处理元件。 相关联的处理元件的数量在列的方向上选择性地变化，以便利用所述信号的并行性。 另外，本发明的处理器体系结构能够实现指令并行性与典型的矢量功能的数据并行处理之间的动态切换。 该架构可以在要执行的算法的最佳配置中以各种尺寸缩放。
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公开(公告)号：US20080016319A1
公开(公告)日：2008-01-17
申请号：US11768481
申请日：2007-06-26
IPC分类号： G06F15/00
CPC分类号： G06F9/3012 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3824 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.
摘要翻译： 用于多媒体应用的处理器架构包括提供矢量数据处理能力的处理器集群。 处理器集群中的处理元件根据单指令多数据（SIMD）功能处理位长度为N的数据和位长度为N / 2，N / 4等的数据。 负载单元根据相同的指令加载到要处理的处理器集群数据中。 集群间数据路径在处理器集群之间交换数据。 集群间数据路径是可扩展的，以激活所选择的处理器集群。 处理器在SIMD，标量和矢量数据上同时运行。
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公开(公告)号：US20080294871A1
公开(公告)日：2008-11-27
申请号：US12130861
申请日：2008-05-30
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F15/8023 , Y02D10/171
摘要： A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational part and a set of associated processing elements that are able to receive the same input signals. The number of associated processing elements is selectively variable in the direction of the column so as to exploit the parallelism of said signals. Additionally the processor architecture of the present invention enable dynamic switching between instruction parallelism and data parallel processing typical of vectorial functionality. The architecture can be scaled in various dimensions in an optimal configuration for the algorithm to be executed.
摘要翻译： 处理器架构包括用于处理输入信号的多个处理元件。 该架构根据包括行和列的矩阵来组织，其列包括至少一个具有计算部分的微处理器块和能够接收相同输入信号的一组相关联的处理元件。 相关联的处理元件的数量在列的方向上选择性地变化，以便利用所述信号的并行性。 另外，本发明的处理器体系结构能够实现指令并行性与典型的矢量功能的数据并行处理之间的动态切换。 该架构可以在要执行的算法的最佳配置中以各种尺寸缩放。
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8.发明申请PROCESS AND DEVICES FOR TRANSMITTING DIGITAL SIGNALS OVER BUSES AND COMPUTER PROGRAM PRODUCT THEREFORE 有权通过业务和计算机程序产品传输数字信号的过程和设备公开(公告)号：US20080211701A1
公开(公告)日：2008-09-04
申请号：US12060809
申请日：2008-04-01
IPC分类号： H03M7/00
CPC分类号： G06F13/4072 , G06F13/4213
摘要： Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.
摘要翻译： 数字信号在给定时刻的总线上以非编码格式和编码格式有选择地发送。 基于在上述给定时刻的总线上发送的信号与总线上的信号发送器的比较，部分地采用以非编码格式或编码格式发送信号的决定 在前一时刻，以便最小化总线上的开关活动。
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9.发明授权Process and devices for transmitting digital signals over buses and computer program product therefore 有权因此，通过总线和计算机程序产品传输数字信号的过程和设备公开(公告)号：US06943706B2
公开(公告)日：2005-09-13
申请号：US10670762
申请日：2003-09-25
CPC分类号： G06F13/4213 , G06F13/4072
摘要： Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format so as to minimize the switching activity on the bus. Given the same value of switching activity, the decision whether to transmit the signals in non-encoded format or in encoded format is taken according to the choice of maintaining constant, without transitions, the value of the additional signal, which signals that encoding of the signals transmitted each time has taken place or has been omitted.
摘要翻译： 数字信号以给定的时刻以非编码格式和编码格式有选择地在总线上传输，以便最小化总线上的切换活动。 给定相同的切换活动值，决定是否以非编码格式或编码格式传输信号是根据维持常数的选择而无转换的，附加信号的值表示信号的编码 每次发生的信号已经发生或已被省略。
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10.发明授权Method and arrangement for cache memory management, related processor architecture 有权高速缓存存储器管理方法与布置，相关处理器架构公开(公告)号：US08078804B2
公开(公告)日：2011-12-13
申请号：US11768462
申请日：2007-06-26
CPC分类号： G06F12/084 , G06F12/0886 , Y02D10/13
摘要： A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.
摘要翻译： 耦合到包括处理器集群的处理器的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供用于存储用于处理的数据的数据位置同时操作标量和矢量数据。 数据位置以标量模式或矢量模式进行访问。 这通过明确地映射标量的数据位置和矢量的数据位置来完成。
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