Abstract:
A liquid crystal display of compact size is disclosed. The liquid crystal display has a tape carrier package and a single integrated PCB for processing a gate driving signal and data driving signal. The tape carrier package includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.
Abstract:
A liquid crystal display of compact size is disclosed. The liquid crystal display has a tape carrier package and a single integrated PCB for processing a gate driving signal and data driving signal. The tape carrier package includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.
Abstract:
A display device includes gate lines transmitting a first gate-on voltage and a second gate-on voltage, data lines transmitting data voltages, pixels including switching elements and pixel electrodes, a gate driver electrically connected to the gate lines and sequentially applying the first and second gate-on voltages to the gate lines, and a data driver applying the data voltages to the data lines. The second gate-on voltage has a magnitude different with a magnitude of the first gate-on voltage. The switching elements are electrically connected to corresponding ones of the gate lines and the data lines. The switching elements are configured to turn on in response to the first and second gate-on voltages. The pixel electrodes are supplied with the data voltages. The gate driver outputs the first gate-on voltage before the second gate-on voltage.
Abstract:
A liquid crystal display has a signal transmission film and a single integrated PCB for processing a gate driving signal and data driving signal. The signal transmission film includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.
Abstract:
A driving unit of a display panel includes a control part, a gate driving part, a grayscale compensating part, and a data driving part. The control part provides a control signal and a grayscale signal. The gate driving part provides a gate signal to the display panel. The display panel is divided into a plurality of blocks according to a distance from a light source to each of the blocks. The grayscale compensating part outputs a compensating signal of an n-th frame using look-up tables, and the look-up tables respectively correspond to the blocks of the display panel. The data driving part converts the compensating signal of the n-th frame into a grayscale voltage and provides the grayscale voltage to the display panel. Accordingly, the driving unit of the display panel may improve a response speed of liquid crystals and display quality.
Abstract:
A film-chip complex includes a film which includes a connection region along one side, a chip which is mounted on the film, a gate signal line which is disposed on the film, wherein the gate signal line includes a gate lead which is disposed in the connection region and a gate main line which connects the chip with the gate lead and a signal line which is disposed on the film, wherein the signal line includes a signal lead which is disposed in the connection region, a signal main line which extends substantially toward an exterior of the connection region and a signal pad which is connected with the signal main line.
Abstract:
A liquid crystal display of compact size is disclosed. The liquid crystal display has a signal transmission film and a single integrated PCB for processing a gate driving signal and data driving signal. The signal transmission film includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.
Abstract:
Liquid crystal display devices include a first row of viewable liquid crystal display cells having data inputs electrically connected to a plurality of data lines (D1-Dn), control gates commonly connected to a first gate line (e.g., G1) and storage capacitors (Cst) having first electrodes electrically connected to a zeroth gate line (e.g., G0). A second row of viewable liquid crystal display cells are also provided having data inputs electrically connected to a plurality of data lines (D1-Dn), control gates commonly connected to a second gate line (e.g., G2) and storage capacitors (Cst) having first electrodes electrically connected to a first gate line (e.g., G1). Moreover, to maintain the RC delay value of the zeroth gate line at a level equal to the RC delay values associated with the higher order gate lines (e.g., G1-Gn), a row of nonviewable or "dummy" liquid crystal display cells are provided having data inputs electrically connected to the plurality of data lines, control gates commonly connected to the zeroth gate line and storage capacitors having first electrodes electrically coupled together. This row of nonviewable cells are provided to "mimic" a row of viewable cells so that the RC delay values associated with the zeroth gate line equals the RC delay value associated with the other gate lines in the array. The row of nonviewable cells may also be replaced by a variable resistance device (e.g., potentiometer, resistor ladder, etc.) and a variable capacitance device which are electrically coupled in series between the zeroth gate line and respective reference potentials (e.g., Vcom, GND, etc.). These variable devices are adjusted so that the total effective RC delay values associated with the zeroth gate line equals the RC delay value associated with the other gate lines.
Abstract:
A driving unit of a display panel includes a control part, a gate driving part, a grayscale compensating part, and a data driving part. The control part provides a control signal and a grayscale signal. The gate driving part provides a gate signal to the display panel. The display panel is divided into a plurality of blocks according to a distance from a light source to each of the blocks. The grayscale compensating part outputs a compensating signal of an n-th frame using look-up tables, and the look-up tables respectively correspond to the blocks of the display panel. The data driving part converts the compensating signal of the n-th frame into a grayscale voltage and provides the grayscale voltage to the display panel. Accordingly, the driving unit of the display panel may improve a response speed of liquid crystals and display quality.
Abstract:
A liquid crystal display of compact size is disclosed. The liquid crystal display has a tape carrier package and a single integrated PCB for processing a gate driving signal and data driving signal. The tape carrier package includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.