公开(公告)号：US10127171B2

公开(公告)日：2018-11-13

申请号：US12874250

申请日：2010-09-02

Applicant: Helmut Reinig ,  Soeren Sonntag

Inventor： Helmut Reinig ,  Soeren Sonntag

IPC: G06F13/40

Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.

公开(公告)号：US09262356B2

公开(公告)日：2016-02-16

申请号：US11640535

申请日：2006-12-15

Applicant: Soren Sonntag ,  Helmut Reinig

Inventor： Soren Sonntag ,  Helmut Reinig

IPC: G06F12/00 ,  G06F13/362

CPC classification number: G06F13/362

Abstract: An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.

Abstract translation: 提出了仲裁在多个输入端口处接收的资源请求的仲裁设备，其包括选择要向其授予资源请求的输入端口的仲裁器电路，并且连续地授权在所选择的输入端口处接收到的多个资源请求。

公开(公告)号：US20150277949A1

公开(公告)日：2015-10-01

申请号：US14227166

申请日：2014-03-27

Applicant: THIAM WAH LOH ,  GAUTHAM N. CHINYA ,  STEPHEN J. ROBINSON ,  REZA FORTAS ,  HONG WANG ,  HELMUT REINIG ,  PER HAMMARLUND ,  DEEPAK A. MATHAIKUTTY ,  CHRISTIAN ERBEN

Inventor： THIAM WAH LOH ,  GAUTHAM N. CHINYA ,  STEPHEN J. ROBINSON ,  REZA FORTAS ,  HONG WANG ,  HELMUT REINIG ,  PER HAMMARLUND ,  DEEPAK A. MATHAIKUTTY ,  CHRISTIAN ERBEN

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/364 ,  G06F12/14

CPC classification number: G06F9/45558 ,  G06F12/145 ,  G06F13/1684 ,  G06F13/364 ,  G06F2009/45587 ,  G06F2212/1052

Abstract: A processing system includes an interconnect and a processing core, coupled to the interconnect, to execute a plurality of virtual machines each being identified by a respective identifier, and tag, by an identifier of the first virtual machine, a first transaction initiated by a first virtual machine to access the interconnect.

Abstract translation: 处理系统包括耦合到互连的互连和处理核，以执行多个虚拟机，每个虚拟机由相应的标识符标识，并且由第一虚拟机的标识符标记由第一虚拟机发起的第一事务 虚拟机访问互连。