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    Data transmission system and method thereof
    11.
    发明申请
    Data transmission system and method thereof 有权
    数据传输系统及其方法

    公开(公告)号：US20090103674A1

    公开(公告)日：2009-04-23

    申请号：US11907859

    申请日：2007-10-18

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: H03D3/24 ,  G09G3/36 ,  H04L7/00

    CPC classification number: G09G3/20 ,  G09G2310/0275 ,  G09G2370/08

    Abstract: A data transmission system includes a transmitter and a receiver. The transmitter mixes an original clock signal and an original data signal to generate and output a hybrid differential signal, the hybrid differential signal having multiple clock pulses and multiple data pulses. At lease one data pulse occurs between two clock pulses, and the period between two clock pulses corresponds to the frequency of the original clock signal. The clock pulses and the data pulses have different differential swings. The receiver receives the hybrid differential signal via a bus and generates a recovered clock signal and a recovered data signal based on the hybrid differential signal. The hybrid differential signal, the original clock signal and the original data signal are reduced swing differential signals.

    Abstract translation: 数据传输系统包括发射机和接收机。 发射机混合原始时钟信号和原始数据信号以产生和输出混合差分信号，混合差分信号具有多个时钟脉冲和多个数据脉冲。 在两个时钟脉冲之间至少发生一个数据脉冲，两个时钟脉冲之间的周期对应于原始时钟信号的频率。 时钟脉冲和数据脉冲具有不同的差分摆幅。 接收机通过总线接收混合差分信号，并根据混合差分信号产生恢复的时钟信号和恢复的数据信号。 混合差分信号，原始时钟信号和原始数据信号是摆幅差分信号。

    Multi-channel receiver, digital edge tuning circuit and method thereof
    12.
    发明授权
    Multi-channel receiver, digital edge tuning circuit and method thereof 失效
    多通道接收机，数字边缘调谐电路及其方法

    公开(公告)号：US07450675B2

    公开(公告)日：2008-11-11

    申请号：US11160526

    申请日：2005-06-28

    Applicant: Hui-Min Wang ,  Chung-Ming Huang ,  Lin-Kai Bu

    Inventor： Hui-Min Wang ,  Chung-Ming Huang ,  Lin-Kai Bu

    IPC: H04L7/00

    CPC classification number: H04L5/023 ,  H04L7/0008 ,  H04L7/033

    Abstract: A multi-channel receiver, digital edge tuning circuit and a method for operating the same is disclosed. The digital edge tuning circuit for tuning phases of an input signal and a clock signal, comprises a delay-tuning circuit for receiving the input signal and delaying the input signal to generate a fine-tuned signal; a delay set comprising a plurality of delays connected serially one by one, the input of the delay set coupled to the fine-tune circuit, for receiving the fine-tuned signal; a plurality of sample/hold circuits, each of the sample/hold circuits coupled to a corresponding output of one of the delays and the fine-tune circuit, for sampling and holding the corresponding output; and a dynamic edge tuning circuit, coupled to the sample/hold circuits, for controlling a common delay time delayed by the delay-tuning circuit according to which one of the sample/hold circuits samples a data edge of the input signal.

    Abstract translation: 公开了一种多通道接收机，数字边缘调谐电路及其操作方法。 用于调谐输入信号和时钟信号的相位的数字边沿调谐电路包括延迟调谐电路，用于接收输入信号并延迟输入信号以产生微调信号; 延迟集合，包括串联地逐个连接的多个延迟，耦合到微调电路的延迟集合的输入，用于接收微调信号; 多个采样/保持电路，每个采样/保持电路耦合到延迟中的一个的对应输出和微调电路，用于采样和保持相应的输出; 以及耦合到采样/保持电路的动态边沿调谐电路，用于根据哪个采样/保持电路对输入信号的数据沿进行采样来控制由延迟调谐电路延迟的公共延迟时间。

    Collapsible container
    13.
    发明申请
    Collapsible container 失效
    可折叠集装箱

    公开(公告)号：US20050061811A1

    公开(公告)日：2005-03-24

    申请号：US10671053

    申请日：2003-09-22

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: B65D5/36 ,  B65D6/12

    CPC classification number: B65D5/3614 ,  B65D2313/02

    Abstract: A collapsible container includes a rectangular bottom, a front and a rear rectangular wall pivotally turnably connected to a front and a rear edge, respectively, of the bottom along two folding lines, two rectangular side walls pivotally turnably connected to two lateral ends of each of the front and the rear wall along two folding lines, and two locating flaps pivotally turnably connected to two lateral edges of the bottom along two folding lines. Each of the two locating flaps is an isosceles triangle having two equal lateral sides separately corresponding to a diagonal of the sidewall. Moreover, fastening elements are correspondingly provided on an inner surface of each side wall and an outer surface of the locating flap to enable detachable connection of the side walls to the locating flaps and accordingly free collapse and extension of the container.

    Abstract translation: 可折叠容器包括矩形底部，前后矩形壁，其分别沿着两条折叠线可转动地连接到底部的前边缘和后边缘，两个矩形侧壁可转动地连接到每个的两个侧端 沿着两条折叠线的前壁和后壁，以及沿两条折叠线可枢转地可转动地连接到底部的两个侧边缘的两个定位翼片。 两个定位翼片中的​​每一个是等腰三角形，其具有分别对应于侧壁的对角线的两个相等的侧边。 此外，紧固元件相应地设置在每个侧壁的内表面和定位翼片的外表面上，以使得侧壁能够与定位翼片可拆卸地连接，并因此自由地使容器的塌缩和延伸。

    Audio clock regenerator with precisely tracking mechanism
    16.
    发明授权
    Audio clock regenerator with precisely tracking mechanism 有权
    音频时钟再生器具有精确的跟踪机制

    公开(公告)号：US08063986B2

    公开(公告)日：2011-11-22

    申请号：US11757829

    申请日：2007-06-04

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: H04N9/475 ,  H04N11/00 ,  H03L7/00

    CPC classification number: H03L7/07 ,  H03L7/235 ,  H04N21/4305

    Abstract: In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock. The tracking circuit tunes the frequency of the crystal clock based on the extracted relationship.

    Abstract translation: 在HDMI系统中，HDMI规范提出的时钟再生器可能会受到外部噪声，因为HDMI系统的信宿设备中的锁相环电路的输入时钟太慢。 这种慢速输入时钟使得锁相环电路不能调节并减少在宿设备中再生的音频时钟的抖动。 因此，本发明的一个实施例提供了一种时钟再生器，用于提取再生的音频时钟与宿设备从其它源设备接收的视频时钟之间的关系。 时钟再生器可以包括锁相环电路，恢复电路，晶体振荡器和跟踪电路。 晶体振荡器产生晶体时钟。 锁相环电路接收晶体钟并重新生成音频时钟。 恢复电路提取音频时钟和接收的视频时钟之间的关系。 跟踪电路根据提取的关系调整晶体时钟的频率。

    Standby circuit and method for a display device
    17.
    发明授权
    Standby circuit and method for a display device 有权
    显示设备的待机电路和方法

    公开(公告)号：US08049696B2

    公开(公告)日：2011-11-01

    申请号：US12326855

    申请日：2008-12-02

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: G09G3/36

    CPC classification number: G09G5/006 ,  G09G2330/022 ,  G09G2370/12

    Abstract: A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.

    Abstract translation: 公开了一种用于显示装置的备用电路和方法。 检测器检测时钟通道的正路径的第一终端电阻器的电压降和负路径的第二终端电阻器。 在检测到电压降时，开关控制器断开具有检测到的电压降的正路径或负路径，从而在显示装置的待机模式下节省功率。

    High frequency surface acoustic wave device and the substrate thereof
    19.
    发明授权
    High frequency surface acoustic wave device and the substrate thereof 有权
    高频声表面波装置及其基板

    公开(公告)号：US07741752B2

    公开(公告)日：2010-06-22

    申请号：US12232033

    申请日：2008-09-10

    Applicant: Wen-Ching Shih ,  Hui-Min Wang

    Inventor： Wen-Ching Shih ,  Hui-Min Wang

    IPC: H03H9/25

    CPC classification number: H03H3/10 ,  H03H9/02574

    Abstract: A high frequency SAW device and the substrate thereof are disclosed. The disclosed high frequency SAW device does not need to use the conventional and expensive sapphire substrate as its substrate. Besides, the disclosed substrate for a high-frequency SAW device can replace the conventional sapphire substrate in the use of the substrate for a high frequency SAW device. The disclosed high frequency SAW device comprises: a substrate; a first buffering layer forming on the surface of the substrate; a second buffering layer forming on the surface of the first buffering layer; a piezoelectric layer forming on the surface of the second buffering layer; an input transformation unit; and an output transformation unit, wherein the input transformation unit and the output transformation unit are formed in pairs on the surface of or beneath the piezoelectric layer.

    Abstract translation: 公开了一种高频SAW器件及其基片。 所公开的高频SAW器件不需要使用常规和昂贵的蓝宝石衬底作为其衬底。 此外，所公开的用于高频SAW器件的衬底可以在使用用于高频SAW器件的衬底时替代传统的蓝宝石衬底。 所公开的高频SAW器件包括：衬底; 形成在所述基板的表面上的第一缓冲层; 形成在所述第一缓冲层的表面上的第二缓冲层; 形成在所述第二缓冲层的表面上的压电层; 输入变换单元; 以及输出变换单元，其中所述输入变换单元和所述输出变换单元成对地形成在所述压电层的表面上或下方。

    Standby Circuit and Method for a Display Device
    20.
    发明申请
    Standby Circuit and Method for a Display Device 有权
    待机电路和显示设备的方法

    公开(公告)号：US20100134391A1

    公开(公告)日：2010-06-03

    申请号：US12326855

    申请日：2008-12-02

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: G09G3/36

    CPC classification number: G09G5/006 ,  G09G2330/022 ,  G09G2370/12

    Abstract: A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.

    Abstract translation: 公开了一种用于显示装置的备用电路和方法。 检测器检测时钟通道的正路径的第一终端电阻器的电压降和负路径的第二终端电阻器。 在检测到电压降时，开关控制器断开具有检测到的电压降的正路径或负路径，从而在显示装置的待机模式下节省功率。

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