公开(公告)号：US20090003075A1

公开(公告)日：2009-01-01

申请号：US12134648

申请日：2008-06-06

Applicant: In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

Inventor： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC: G11C16/06

CPC classification number: G11C16/10

Abstract: A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

Abstract translation: 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

公开(公告)号：US20080170443A1

公开(公告)日：2008-07-17

申请号：US12003589

申请日：2007-12-28

Applicant: Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

Inventor： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC: G11C16/06

CPC classification number: G11C16/3454

Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

Abstract translation: 闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中， 验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。

公开(公告)号：US20060291290A1

公开(公告)日：2006-12-28

申请号：US11381140

申请日：2006-05-02

Applicant: Soo-Han Kim ,  Jae-Yong Jeong

Inventor： Soo-Han Kim ,  Jae-Yong Jeong

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C16/3454 ,  G11C16/3459

Abstract: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.

Abstract translation: 非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。 一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。 非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。 控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于 验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有低于第一个字线的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线 步高。

公开(公告)号：US07123528B2

公开(公告)日：2006-10-17

申请号：US10677841

申请日：2003-10-01

Applicant: Jae-Yong Jeong ,  Heung-Soo Lim

Inventor： Jae-Yong Jeong ,  Heung-Soo Lim

IPC: G11C29/00

CPC classification number: G11C29/34 ,  G11C8/12 ,  G11C16/04 ,  G11C2029/1204 ,  G11C2029/2602

Abstract: A column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.

Abstract translation: 列预解码器包括用于输入所有列选择信号的缓冲单元，用于对缓冲单元和列地址的输出进行解码的解码器单元和用于响应于列选择晶体管的栅极耦合到列选择晶体管的列选择信号的电压电平的电平移位器 解码器单元的输出。 由于接地电压施加于位线，并且在应力测试期间对所有列选择信号施加高电压，所以可以缩短应力测试时间。

公开(公告)号：US20060104104A1

公开(公告)日：2006-05-18

申请号：US11247839

申请日：2005-10-11

Applicant: Jae-Woo Park ,  Jae-Yong Jeong

Inventor： Jae-Woo Park ,  Jae-Yong Jeong

IPC: G11C17/00

CPC classification number: G11C16/3468

Abstract: Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to at least two word lines coupled to ones of the plurality of erased memory cells of the memory cell array. Related devices are also discussed.

Abstract translation: 存储单元阵列中的存储单元将使用擦除操作，随后进行后期程序擦除。 在擦除操作中，擦除电压被施加到存储单元阵列的多个存储单元。 在后期编程操作中，将编程电压同时施加到与存储单元阵列的多个被擦除的存储单元中的一个相连的至少两个字线。 还讨论了相关设备。

公开(公告)号：US20060087891A1

公开(公告)日：2006-04-27

申请号：US11257074

申请日：2005-10-25

Applicant: Jae-Yong Jeong ,  Heung-Soo Lim

Inventor： Jae-Yong Jeong ,  Heung-Soo Lim

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/24

Abstract: Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

Abstract translation: 公开了一种非易失性存储器件及其编程方法。 该方法包括在多个程序循环期间将字线电压，位线电压和体电压施加到存储器单元。 在当前程序循环期间位线电压下降到低于第一预定检测电压或体电压变得高于第二预定检测电压的情况下，在当前编程环路中使用相同的字线电压，并在下一个程序循环 当前程序循环。 否则，在下一个编程循环之前，字线电压增加预定量。

公开(公告)号：US20060067130A1

公开(公告)日：2006-03-30

申请号：US11017335

申请日：2004-12-20

Applicant: Jae-Yong Jeong

Inventor： Jae-Yong Jeong

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/3436

Abstract: Data verification methods and/or nonvolatile memory devices are provided that concurrently detect data for a selected memory cell of the nonvolatile memory device and verify a programmed or erase state of previously detected data of a different memory cell of the nonvolatile memory device. Concurrently detecting data and verifying a programmed or erase state may be provided by a sense amplifier configured to sense data from a memory cell of the nonvolatile memory device, a latch configured to store the data sensed by the sense amplifier, an I/O buffer configured to store the data stored in the latch and a program/erase verifier circuit configured to control the sense amplifier, latch and I/O buffer to provided previously sensed data for a first memory cell to the program erase/verifier circuit for verification while the sense amplifier is sensing data for a second memory cell.

Abstract translation: 提供了数据验证方法和/或非易失性存储器件，其同时检测非易失性存储器件的选定存储单元的数据，并验证非易失性存储器件的不同存储单元的先前检测到的数据的编程或擦除状态。 同时检测数据和验证编程或擦除状态可以由配置成感测来自非易失性存储器件的存储单元的数据的读出放大器提供，配置成存储读出放大器检测到的数据的锁存器，配置的I / O缓冲器 存储在锁存器中的数据和编程/擦除验证器电路，其被配置为控制读出放大器，锁存器和I / O缓冲器，以将第一存储器单元的先前检测到的数据提供给程序擦除/验证器电路以进行验证 放大器感测第二存储单元的数据。

公开(公告)号：US06717861B2

公开(公告)日：2004-04-06

申请号：US10006196

申请日：2001-12-04

Applicant: Jae-Yong Jeong ,  Sung-Soo Lee

Inventor： Jae-Yong Jeong ,  Sung-Soo Lee

IPC: G11C1604

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.

Abstract translation: 公开了一种非易失性半导体存储器件，其包括根据位线设置，串选择线设置，编程周期的编程和放电周期来控制选择线和字线的电位的电路。 控制电路在编程周期中的位线建立期间将串选择线偏置为电源电压，并且在串选择线设置和程序周期期间将电源电压和接地电压之间的电压偏置。 根据串选择线控制方案，防止当将编程电压施加到与串选择线相邻的字线时在串选择线处感应到的噪声电压时的程序干扰。

公开(公告)号：US06614688B2

公开(公告)日：2003-09-02

申请号：US09990191

申请日：2001-11-20

Applicant: Jae-Yong Jeong ,  Jin-Seon Yeom ,  Sung-Soo Lee

Inventor： Jae-Yong Jeong ,  Jin-Seon Yeom ,  Sung-Soo Lee

IPC: G11C1604

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area. In the program step, a program voltage is supplied to selected wordlines and a pass voltage is supplied to unselected wordlines, with the floating second well area biased with the coupling voltage. Therefore, the pocket P-well area is biased with a negative voltage through the capacitance coupling.

公开(公告)号：US06353555B1

公开(公告)日：2002-03-05

申请号：US09597174

申请日：2000-06-20

Applicant: Jae-Yong Jeong

Inventor： Jae-Yong Jeong

IPC: G11C1134

CPC classification number: G11C16/08

Abstract: Disclosed is a nonvolatile semiconductor memory device which comprises a controller for controlling block select signal generators. The controller simultaneously activates the block select signal generators in a bit line setup and a recovery period, so that the word lines in each of memory blocks are set to a predetermined voltage (for example, a ground voltage, a power supply voltage, or an intermediate voltage), respectively. According to the control scheme, by attenuating a bouncing of a substrate voltage caused in an instant by means of a capacitive coupling between a bit line and a substrate at a transition of a bit line voltage, there are prevented an under program and a program disturb during a program cycle.

Abstract translation: 公开了一种非易失性半导体存储器件，其包括用于控制块选择信号发生器的控制器。 控制器在位线设置和恢复周期中同时激活块选择信号发生器，使得每个存储器块中的字线被设置为预定电压（例如，接地电压，电源电压或 中间电压）。 根据该控制方案，通过在位线电压的转变下借助于位线与衬底之间的电容耦合来瞬间引起的衬底电压的跳动，防止了程序和程序干扰 在程序周期。