公开(公告)号：US07376004B2

公开(公告)日：2008-05-20

申请号：US10661448

申请日：2003-09-11

Applicant: James R. Eaton, Jr. ,  Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

Inventor： James R. Eaton, Jr. ,  Frederick A. Perner ,  Lung T. Tran ,  Kenneth J. Eldredge

IPC: G11C11/00 ,  G11C11/14

CPC classification number: G11C11/16

Abstract: A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.

Abstract translation: 用于制造磁随机存取存储器（MRAM）的方法在操作期间隔离MRAM阵列中的每个存储单元直到被选择。 一些实施例使用用于这种电隔离的串联连接的二极管。 只有选定的一个存储器单元将在相应的位和字线之间传导电流。 读取和写入数据访问电流的更好，更均匀的分布会导致所有存储单元。 在另一个实施例中，该改进用于增加支持较大数据阵列的行数和列数。 在另一实施例中，这种改进用于增加操作裕度并减少必要的数据写入电压和电流。

公开(公告)号：US06864529B2

公开(公告)日：2005-03-08

申请号：US09934548

申请日：2001-08-23

Applicant: Ping Mei ,  James R. Eaton, Jr.

Inventor： Ping Mei ,  James R. Eaton, Jr.

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/02 ,  G11C17/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C17/16

Abstract: A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator. The gate electrode portion includes a diffusive conductor that diffuses through the insulator under the application of a write voltage. The diffusive conductor forms a conductive path through the insulator that couples the gate line to the floating gate, changing the gate capacitance and therefore the state of the memory cell. The states of the memory cells are detectable as the differing current values for the memory cells. The memory cells are three terminal devices, and read currents do not pass through the conductive paths in the memory cells during read operations. This renders the memory cells robust, because read currents will not interfere with the storage mechanism in the memory cells. The memory array can be fabricated using multiple steps using the same mask. The use of a single mask for multiple steps reduces the time and cost involved in fabricating the memory array.