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公开(公告)号：US07376004B2
公开(公告)日：2008-05-20
申请号：US10661448
申请日：2003-09-11
CPC分类号： G11C11/16
摘要： A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.
摘要翻译： 用于制造磁随机存取存储器（MRAM）的方法在操作期间隔离MRAM阵列中的每个存储单元直到被选择。 一些实施例使用用于这种电隔离的串联连接的二极管。 只有选定的一个存储器单元将在相应的位和字线之间传导电流。 读取和写入数据访问电流的更好，更均匀的分布会导致所有存储单元。 在另一个实施例中，该改进用于增加支持较大数据阵列的行数和列数。 在另一实施例中，这种改进用于增加操作裕度并减少必要的数据写入电压和电流。
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2.发明授权Triple sample sensing for magnetic random access memory (MRAM) with series diodes 有权具有串联二极管的磁性随机存取存储器（MRAM）的三次采样检测公开(公告)号：US06873544B2
公开(公告)日：2005-03-29
申请号：US10696826
申请日：2003-10-30
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15 , G11C11/16 , G11C13/004 , G11C27/02 , G11C2013/0057
摘要： A data storage device that includes an array of resistive memory cells. The resistive memory cells may include a magnetic tunnel junction (MTJ) and a thin-film diode. The device may include a circuit that is electrically connected to the array and that is also capable of monitoring a signal current flowing through a selected memory cell. Once the signal current has been monitored, the circuit is capable of comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the selected memory cell is in. Also, a method for operating the data storage device.
摘要翻译： 一种包括电阻式存储单元阵列的数据存储装置。 电阻存储单元可以包括磁性隧道结（MTJ）和薄膜二极管。 该装置可以包括电连接到阵列的电路，并且还能够监测流过所选择的存储器单元的信号电流。 一旦已经监视了信号电流，电路就可以将信号电流与平均参考电流进行比较，以确定所选择的存储单元处于第一电阻状态和第二电阻状态。另外，一种操作方法 数据存储设备。
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公开(公告)号：US06757188B2
公开(公告)日：2004-06-29
申请号：US10151915
申请日：2002-05-22
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C11/16 , G11C13/004 , G11C27/02 , G11C2013/0057
摘要： A data storage device that includes an array of resistive memory cells. The resistive memory cells may include a magnetic tunnel junction (MTJ) and a thin-film diode. The device may include a circuit that is electrically connected to the array and that is also capable of monitoring a signal current flowing through a selected memory cell. Once the signal current has been monitored, the circuit is capable of comparing the signal current to an average reference current in order to determine which of a first resistance state and a second resistance state the selected memory cell is in. Also, a method for operating the data storage device.
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公开(公告)号：US06262625B1
公开(公告)日：2001-07-17
申请号：US09430238
申请日：1999-10-29
IPC分类号： G01R1900
CPC分类号： B82Y10/00 , G11C11/15 , H03F1/304 , H03F3/45771 , H03F2203/45048 , H03F2203/45291 , H03F2203/45342 , H03F2203/45624 , H03F2203/45726
摘要： An operational amplifier includes transistors for providing a controlled current path. At least one of the transistors is in an isolated well in a substrate. Offset of the operational amplifier is corrected by applying a back gate bias voltage to at least one isolated well and changing impedance of the transistors. The proper back gate bias voltage and transistor impedance are determined by incrementally adjusting the back gate bias voltage and then incrementally adjusting the transistor impedance. Calibration values are stored in register memory. Such calibration may be performed by an auto offset calibration process.
摘要翻译： 运算放大器包括用于提供受控电流路径的晶体管。 至少一个晶体管处于衬底中的隔离阱中。 通过对至少一个隔离阱施加背栅偏置电压并改变晶体管的阻抗来校正运算放大器的偏移。 正确的背栅偏置电压和晶体管阻抗通过逐步调整背栅偏置电压然后逐渐调整晶体管阻抗来确定。 校准值存储在寄存器存储器中。 这种校准可以通过自动偏移校准过程来执行。
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公开(公告)号：US06188615B1
公开(公告)日：2001-02-13
申请号：US09430611
申请日：1999-10-29
IPC分类号： G11C1604
摘要： Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and a digital sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier measures integration time of a signal on the integrator. The signal integration time indicates whether the memory cell MRAM resistance is at a first state (R) or a second state (R+&Dgr;R).
摘要翻译： 通过包括直接注入电荷放大器，积分器电容器和数字读出放大器的读取电路来检测磁性随机存取存储器（“MRAM”）器件中的所选存储单元的电阻。 直接注入电荷放大器向积分器电容器提供电流，同时在MRAM器件中的未选择的存储单元上保持等电位电压。 由于直接注入电荷放大器对所选择的存储单元施加固定电压，所以读出放大器测量积分器上信号的积分时间。 信号积分时间表示存储单元MRAM电阻是处于第一状态（R）还是第二状态（R + DELTAR）。
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公开(公告)号：US06534841B1
公开(公告)日：2003-03-18
申请号：US10017567
申请日：2001-12-14
申请人： Andrew L. Van Brocklin , Kenneth J. Eldredge , S. Jonathan Wang , Frederick A Perner , Peter Fricke
发明人： Andrew L. Van Brocklin , Kenneth J. Eldredge , S. Jonathan Wang , Frederick A Perner , Peter Fricke
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L27/10 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs. Furthermore the present invention includes a memory structure comprising a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with a plurality of control elements.
摘要翻译： 存储器结构具有未图案化并夹在多个反熔丝电极对中的每一个之间的反熔丝材料。 反熔丝材料在反熔丝电极对之间是连续的。 此外，本发明包括一种存储结构，该存储结构包括形成多个行导体的多个反熔丝电极对以及与多个控制元件电连通的多个中间导体。
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7.发明授权公开(公告)号：US07535754B2
公开(公告)日：2009-05-19
申请号：US11264539
申请日：2005-11-01
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A memory device and method of reading the memory device is disclosed. The memory device includes a first string of MRAM cells and a second string of MRAM cells. The first string of MRAM cells include a plurality of MRAM cells connected in series and the second string of MRAM cells include another plurality of MRAM cells connected in series. A common connection is controllably connectable to one end of the first string of MRAM cells, and to one end of the second string of MRAM cells.
摘要翻译： 公开了一种读取存储器件的存储器件和方法。 存储器件包括MRAM单元的第一串和MRAM单元的第二串。 MRAM单元的第一串包括串联连接的多个MRAM单元，并且第二串MRAM单元包括串联连接的另外多个MRAM单元。 公共连接可控地连接到MRAM单元的第一串的一端，并连接到第二串MRAM单元的一端。
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公开(公告)号：US06317376B1
公开(公告)日：2001-11-13
申请号：US09598671
申请日：2000-06-20
申请人： Lung T. Tran , Kenneth J. Eldredge
发明人： Lung T. Tran , Kenneth J. Eldredge
IPC分类号： G11C702
摘要： A Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells. The device generates reference signals that can be used to determine the resistance states of each memory cell in the array, despite variations in resistance due to manufacturing tolerances and other factors such as temperature gradients across the array, electromagnetic interference and aging.
摘要翻译： 磁性随机存取存储器（“MRAM”）装置包括一组存储单元。 该器件产生可用于确定阵列中每个存储单元的电阻状态的参考信号，尽管由于制造公差和其他因素（例如阵列上的温度梯度，电磁干扰和衰老）导致的电阻变化。
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公开(公告)号：US06927996B2
公开(公告)日：2005-08-09
申请号：US10676465
申请日：2003-09-30
IPC分类号： G11C11/15 , G11C7/00 , G11C7/12 , G11C11/14 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： A magnetic random access memory (MRAM) includes an array of magnetic memory cells arranged on a cross-point grid. Spurious voltages that build up on the stray wiring capacitance of unselected bit and word select lines are limited and discharged by diodes. The control of such spurious voltages improves device operating margins and allows the construction of larger arrays.
摘要翻译： 磁性随机存取存储器（MRAM）包括布置在交叉点网格上的磁存储器单元的阵列。 在未选择位和字选择线的杂散布线电容上形成的杂散电压受到二极管的限制和放电。 这种杂散电压的控制提高了器件工作裕度，并允许构建更大的阵列。
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公开(公告)号：US06728799B1
公开(公告)日：2004-04-27
申请号：US09483383
申请日：2000-01-13
IPC分类号： G06F1314
CPC分类号： G11C7/1006 , G11C7/1036 , G11C19/00
摘要： Some forms of memory data I/O requires a parallel interface with the memory array and a serial interface with external data ports to the memory. A hybrid decoder/scan register data I/O scheme is described that offers a high speed data access to selected points along a set of scan registers that connect to the columns (bit lines) of a memory array. The interface to the memory array is a long register which comprises a chain of scan register blocks. Data to and from the memory array is transferred in a parallel manner. Data I/O to a specific memory address or memory data block is routed from a serial data I/O line, through a set of switches controlled by a decoder circuit to the input (or output) port of one of the scan register blocks. This hybrid data I/O circuit offers a high speed access to selected points within the column circuits of a memory array while maintaining an efficient and high speed serial output offered by a scan chain data register.
摘要翻译： 存储器数据I / O的一些形式需要与存储器阵列的并行接口以及与存储器的外部数据端口的串行接口。 描述了混合解码器/扫描寄存器数据I / O方案，其提供了沿着连接到存储器阵列的列（位线）的一组扫描寄存器的选定点的高速数据访问。 与存储器阵列的接口是长寄存器，其包括一连串的扫描寄存器块。 往返于存储器阵列的数据以并行方式传送。 特定存储器地址或存储器数据块的数据I / O从串行数据I / O线通过由解码器电路控制的一组开关路由到其中一个扫描寄存器块的输入（或输出）端口。 该混合数据I / O电路提供对存储器阵列的列电路内的选定点的高速访问，同时保持由扫描链数据寄存器提供的有效和高速的串行输出。
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