公开(公告)号：US06303491B1

公开(公告)日：2001-10-16

申请号：US09283984

申请日：1999-04-02

Applicant: Tzu-Ching Tsai ,  Lin-Chin Su ,  Jengping Lin ,  Tse Yao Huang

Inventor： Tzu-Ching Tsai ,  Lin-Chin Su ,  Jengping Lin ,  Tse Yao Huang

IPC: H01L214763

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76831

Abstract: A method for fabricating a self-aligned contact hole in accordance with the present invention is disclosed. First a conductive layer, a silicon oxide layer, and a first silicon nitride layer are formed on a silicon substrate. Next, the first silicon nitride layer, the silicon oxide layer, and the conductive layer are etched to form a trench. Then, a BPSG layer is formed over the first silicon nitride layer. A photoresist layer having an opening is defined. Then, using the photoresist layer as the masking layer, a part of BPSG layer is etched to form a self-aligned hole. Next, the photoresist layer is removed. Afterward, a second silicon nitride layer is formed and etched back to form a spacer.

Abstract translation: 公开了一种用于制造根据本发明的自对准接触孔的方法。 首先，在硅衬底上形成导电层，氧化硅层和第一氮化硅层。 接下来，蚀刻第一氮化硅层，氧化硅层和导电层以形成沟槽。 然后，在第一氮化硅层上形成BPSG层。 定义了具有开口的光刻胶层。 然后，使用光致抗蚀剂层作为掩模层，对BPSG层的一部分进行蚀刻以形成自对准孔。 接下来，去除光致抗蚀剂层。 之后，形成第二氮化硅层并将其回蚀以形成间隔物。

公开(公告)号：US5641698A

公开(公告)日：1997-06-24

申请号：US592152

申请日：1996-04-25

Applicant: Jengping Lin

Inventor： Jengping Lin

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/6659 ,  H01L21/823468 ,  H01L29/435 ,  H01L29/6656 ,  H01L29/7836 ,  H01L29/49 ,  Y10S257/90

Abstract: An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

Abstract translation: 一种改进的FET器件，其中热载流子抗扰度和电流驱动能力得到改善，并且亚阈值泄漏电流最小化。 该器件具有具有垂直侧壁的栅电极和电极上的SiO 2薄层。 第一多晶硅间隔物设置在垂直侧壁上，在第一间隔物上方具有第二上覆氧化物间隔物。 栅电极和多晶硅间隔物之间​​的SiO 2层的顶部部分被制成足够导电以保持栅电极和多晶硅间隔物处于相同的电位。 提供了轻掺杂的源极和漏极区域。

公开(公告)号：US5550079A

公开(公告)日：1996-08-27

申请号：US490832

申请日：1995-06-15

Applicant: Jengping Lin

Inventor： Jengping Lin

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/283

CPC classification number: H01L21/823842 ,  H01L21/76889

Abstract: A method for fabricating a silicide shunt for use in dual-gate CMOS devices makes use of a nitrogen-containing silicide layer overlying the juncture between the P-type polysilicon layer and the N-type polysilicon layer. The nitrogen-containing silicide layer is formed by implanting nitrogen-containing ions, such as .sup.28 N.sub.2.sup.+, into a partial or overall silicide shunt which was originally deposited over the P-type polysilicon layer and N-type polysilicon layer. Therefore, the nitrogen-containing silicide layer can serve as a diffusion barrier layer retarding the lateral dopant diffusion of these polysilicon layers via the silicide shunt.

Abstract translation: 用于制造用于双栅极CMOS器件的硅化物分流器的方法利用覆盖在P型多晶硅层和N型多晶硅层之间的接合处的含氮硅化物层。 含氮硅化物层通过将诸如28N2 +的含氮离子注入到最初沉积在P型多晶硅层和N型多晶硅层上的部分或全部硅化物分流器中而形成。 因此，含氮硅化物层可以用作通过硅化物分路延迟这些多晶硅层的横向掺杂剂扩散的扩散阻挡层。

公开(公告)号：US5550074A

公开(公告)日：1996-08-27

申请号：US591236

申请日：1996-01-19

Applicant: Jengping Lin

Inventor： Jengping Lin

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/6659 ,  H01L29/1083 ,  H01L29/7833 ,  Y10S148/106 ,  Y10S148/137 ,  Y10S438/948

Abstract: Disclosed is a semiconductor fabrication process for fabricating MOS transistors in which ions are implanted only beneath the channel and are not overlapped with the source/drain regions so as to significantly reduce the junction capacitance of the source/drain regions for performance enhancement. The process comprises a first step of preparing a silicon substrate on which a field oxide region is formed to define an active region. In the second step, a phase-shift mask is used to define a substantially rectangular removal portion on a photoresist layer. One side of the rectangular removal portion is substantially aligned with the channel of the MOS transistor to be fabricated and the other three sides are placed within the field oxide region. In the third step, an anti-punchthrough implantation process is performed, in which ions are implanted through the removal portion of the photoresist layer to form an anti-punchthrough implant region beneath the channel of the MOS transistor; and in the final step, a gate region and source/drain regions are formed. The thus formed anti-punchthrough implant region is right beneath the channel of the MOS transistor and does not overlap with the source/drain regions. The packing density and performance of chips containing MOS transistors thus fabricated are high.

Abstract translation: 公开了用于制造MOS晶体管的半导体制造工艺，其中离子仅注入沟道下方并且不与源极/漏极区重叠，以便显着降低源极/漏极区的结电容以提高性能。 该方法包括制备其上形成有场氧化物区域以限定有源区的硅衬底的第一步骤。 在第二步骤中，使用相移掩模来限定光致抗蚀剂层上的大致矩形的去除部分。 矩形去除部分的一侧基本上与待制造的MOS晶体管的沟道对准，而另外三个侧面放置在场氧化物区域内。 在第三步骤中，进行抗穿透注入工艺，其中通过光致抗蚀剂层的去除部分注入离子，以在MOS晶体管的沟道下面形成抗穿透注入区域; 并且在最后的步骤中，形成栅极区域和源极/漏极区域。 如此形成的抗穿透注入区域正好位于MOS晶体管的沟道正下方，并且不与源/漏区重叠。 由此制造的包含MOS晶体管的芯片的封装密度和性能很高。

公开(公告)号：US5547900A

公开(公告)日：1996-08-20

申请号：US450891

申请日：1995-05-26

Applicant: Jengping Lin

Inventor： Jengping Lin

IPC: H01L21/28 ,  H01L21/316

CPC classification number: H01L21/28 ,  H01L21/316

Abstract: This invention provides a method of fabricating a self-aligned contact of a semiconductor device using a liquid-phase oxide-deposition (LPD) process. A gate electrode and source/drain regions are formed on a semiconductor substrate. A layer of photoresist is coated and patterned overlying an area of the semiconductor substrate that will form a contact. Using the photoresist as a mask, an oxide layer is formed in self-aligned manner by a liquid-phase deposition process. The photoresist is removed to expose a contact portion of the source/drain regions. An interlevel conductive layer is formed on the semiconductor substrate, wherein the interlevel conductive layer is connected to the source/drain regions through the contact portion.

Abstract translation: 本发明提供使用液相氧化物沉积（LPD）工艺制造半导体器件的自对准接触的方法。 在半导体衬底上形成栅电极和源/漏区。 将一层光致抗蚀剂涂覆并图案化，覆盖将形成接触的半导体衬底的区域。 使用光致抗蚀剂作为掩模，通过液相沉积工艺以自对准的方式形成氧化物层。 去除光致抗蚀剂以露出源/漏区的接触部分。 在半导体衬底上形成层间导电层，其中层间导电层通过接触部分连接到源/漏区。