公开(公告)号：US6093639A

公开(公告)日：2000-07-25

申请号：US739853

申请日：1996-10-30

Applicant: Clint Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Clint Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76864 ,  H01L21/76843

Abstract: A process for fabricating contact plugs for semiconductor IC devices. An insulating layer is formed over the surface of an IC substrate. The insulating layer is then patterned for forming contact vias revealing the surface of an electrically conductive region of the IC circuitry that requires electrical connections by the contact plugs. A glue (adhesive) layer is then formed over the sidewall surface inside the contact vias. The glue (adhesive) layer is densified by either a rapid thermal annealing or a plasma treatment in order to prevent the formation of voids when the plugs are formed. The internal space of the contact vias are then filled with an electrically conductive material to form the contact plugs. The surface of the device substrate is then polished to remove the electrically conductive material and glue layer covering the surface of the insulating layer until the insulating layer surface is exposed, and top surface of the formed contact plug is planarized flat with the surface of the insulating layer.

Abstract translation: 一种用于制造用于半导体IC器件的接触插塞的工艺。 在IC基板的表面上形成绝缘层。 然后对绝缘层进行图案化，以形成接触通孔，该接触通孔显示IC电路的导电区域的表面，该导电区域需要通过接触插头进行电连接。 然后在接触通孔内部的侧壁表面上形成胶（粘合剂）层。 胶粘剂（粘合剂）层通过快速热退火或等离子体处理来致密化，以防止在形成插塞时形成空隙。 然后用导电材料填充接触孔的内部空间以形成接触塞。 然后抛光器件衬底的表面以去除覆盖绝缘层的表面的导电材料和胶层，直到绝缘层表面露出，并且形成的接触插塞的顶表面与绝缘体的表面平坦化 层。

公开(公告)号：US5950108A

公开(公告)日：1999-09-07

申请号：US768855

申请日：1996-12-17

Applicant: Clint Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Clint Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76862 ,  H01L21/76843 ,  H01L21/76877

Abstract: A method of forming a conductive plug is disclosed. A device with a conductive region is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. The insulating layer is etched to form a contact window which exposes the conductive region of the device. A diffusion barrier layer is formed on the exposed conductive region and the periphery of the contact window. A hydrogen plasma treatment is performed in a reaction chamber; and a conductive material is filled in the contact window, to form the conductive plug.

Abstract translation: 公开了一种形成导电插塞的方法。 具有导电区域的器件形成在半导体衬底上。 绝缘层形成在半导体衬底上。 绝缘层被蚀刻以形成暴露该器件的导电区域的接触窗口。 在暴露的导电区域和接触窗的周边上形成扩散阻挡层。 在反应室中进行氢等离子体处理; 并且导电材料填充在接触窗口中，以形成导电插塞。

公开(公告)号：US5716888A

公开(公告)日：1998-02-10

申请号：US654779

申请日：1996-05-29

Applicant: Water Lur ,  Jenn-Tarng Lin ,  Her-Song Liaw

Inventor： Water Lur ,  Jenn-Tarng Lin ,  Her-Song Liaw

IPC: H01L23/31 ,  H01L23/532 ,  H01L21/56

CPC classification number: H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/958

Abstract: A new method of forming controlled voids within the intermetal dielectric and within the passivation layer of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the first patterned metal layer wherein the thickness of the intermetal dielectric layer is large enough so as to cause the formation of voids within the intermetal dielectric and wherein said voids are completely covered by said intermetal dielectric. A second layer of metallization is deposited over the intermetal dielectric and patterned. A passivation layer is deposited overlying the second patterned metal layer. The thickness of the passivation layer is large enough so as to cause the formation of voids within the passivation layer wherein said voids are completely covered by said passivation layer. The thermal stresses are released by the voids within the intermetal dielectric and within the passivation layer of the integrated circuit.

Abstract translation: 实现了在金属间电介质内和集成电路的钝化层内形成受控空隙的新方法。 在半导体衬底上和半导体衬底上的半导体器件结构上提供第一层图案化金属化层。 沉积金属间电介质层，覆盖第一图案化金属层，其中金属间电介质层的厚度足够大以便在金属间电介质内形成空隙，并且其中所述空隙被所述金属间电介质完全覆盖。 第二层金属化层沉积在金属间电介质上并图案化。 沉积在第二图案化金属层上的钝化层。 钝化层的厚度足够大以便在钝化层内形成空隙，其中所述空隙被所述钝化层完全覆盖。 热应力由金属间电介质内的空隙和集成电路的钝化层释放。

公开(公告)号：US5466627A

公开(公告)日：1995-11-14

申请号：US214608

申请日：1994-03-18

Applicant: Water Lur ,  Jenn-Tarng Lin ,  Hsiaw-Sheng Chin

Inventor： Water Lur ,  Jenn-Tarng Lin ,  Hsiaw-Sheng Chin

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S438/947

Abstract: A MOST capacitor for use in a DRAM is formed by using BPSG precipitates after densification as a mask for etching a BPSG layer to form BPSG islands. The BPSG islands are then used as a mask for etching a polysilicon layer to form pillars in the polysilicon layer.

Abstract translation: 用于DRAM的MOST电容器通过使用致密化后的BPSG沉淀物作为蚀刻BPSG层以形成BPSG岛的掩模形成。 然后将BPSG岛用作蚀刻多晶硅层的掩模，以在多晶硅层中形成柱。