公开(公告)号：US6146742A

公开(公告)日：2000-11-14

申请号：US34793

申请日：1998-03-03

Applicant: Wen-Yi Hsieh ,  Chi-Rong Lin ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Wen-Yi Hsieh ,  Chi-Rong Lin ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/28 ,  H01L29/49 ,  H01L23/48

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/31678

Abstract: A method for forming a barrier/glue layer above the polysilicon layer of a MOS transistor gate comprising the step of providing a semiconductor substrate, and then forming a gate oxide layer above the substrate. Next, a polysilicon layer is formed over the gate oxide layer. Thereafter, a titanium layer is deposited over the polysilicon layer first, and then a titanium nitride layer is deposited above the titanium layer. This titanium/titanium nitride bi-layer is capable of increasing the adhesive strength with a subsequently deposited tungsten silicide layer, and preventing the peeling of the tungsten silicide layer. Furthermore, the titanium nitride layer acts as a barrier for fluorine atoms preventing their diffusion to the gate oxide layer/polysilicon layer interface, and affecting the effective thickness of the gate oxide layer. In the subsequent step, a tungsten suicide layer is formed above the titanium nitride layer. Finally, after an annealing operation, the titanium layer will react with the silicon in the polysilicon layer and the tungsten silicide layer to form a titanium silicide layer. Hence, the resistance of the polycide layer in a MOS transistor gate can be reduced.

Abstract translation: 一种用于在MOS晶体管栅极的多晶硅层上形成阻挡/胶合层的方法，包括提供半导体衬底，然后在衬底上形成栅氧化层的步骤。 接下来，在栅极氧化物层上形成多晶硅层。 此后，首先在多晶硅层上沉积钛层，然后在钛层上方沉积氮化钛层。 该钛/氮化钛双层能够随后沉积的硅化钨层增加粘合强度，并且防止硅化钨层的剥离。 此外，氮化钛层用作氟原子的阻挡层，防止其扩散到栅极氧化物层/多晶硅层界面，并影响栅极氧化物层的有效厚度。 在随后的步骤中，在氮化钛层的上方形成硅化钨层。 最后，在退火操作之后，钛层将与多晶硅层中的硅和硅化钨层反应形成硅化钛层。 因此，可以降低MOS晶体管栅极中的多晶硅化物层的电阻。

公开(公告)号：US5897373A

公开(公告)日：1999-04-27

申请号：US870822

申请日：1997-06-06

Applicant: Yuan-Ching Peng ,  Lih-Juann Chen ,  Wen-Yi Hsieh ,  Jenn-Tarng Lin ,  Yong-Fen Hsieh

Inventor： Yuan-Ching Peng ,  Lih-Juann Chen ,  Wen-Yi Hsieh ,  Jenn-Tarng Lin ,  Yong-Fen Hsieh

IPC: H01L21/285 ,  H01L21/283

CPC classification number: H01L21/28518

Abstract: The present invention relates to a method of manufacturing semiconductor components having a titanium nitride layer including the steps of providing a semiconductor substrate with a transistor including a gate and source/drain regions, depositing an insulating layer above the semiconductor substrate, etching the insulating layer to form an opening exposing the source/drain region below, depositing an ultra-thin titanium nitride layer having a grainy particulate profile and a thickness of about 0.5 nm to 2 nm around the edge and at the bottom of the opening, depositing a metallic layer over various aforementioned layers, and forming a metal silicide layer by heating the semiconductor substrate to allow the metallic layer to react with silicon on the semiconductor substrate surface.

Abstract translation: 本发明涉及一种制造具有氮化钛层的半导体元件的方法，包括以下步骤：向半导体衬底提供包括栅极和源/漏区的晶体管，在半导体衬底上沉积绝缘层，将绝缘层蚀刻到 形成暴露下面的源极/漏极区域的开口，在开口的边缘和底部沉积具有粒状颗粒轮廓和约0.5nm至2nm的厚度的超薄氮化钛层，沉积金属层 各种上述层，并且通过加热半导体衬底形成金属硅化物层，以允许金属层与半导体衬底表面上的硅反应。

公开(公告)号：US5292680A

公开(公告)日：1994-03-08

申请号：US57883

申请日：1993-05-07

Applicant: Water Lur ,  J. Y. Wu ,  Jenn-Tarng Lin

Inventor： Water Lur ,  J. Y. Wu ,  Jenn-Tarng Lin

IPC: H01L21/306 ,  H01L21/339 ,  H01L29/10 ,  H01L29/768

CPC classification number: H01L29/66954 ,  H01L21/306 ,  H01L29/1062 ,  H01L29/76833 ,  Y10S438/911 ,  Y10S438/981

Abstract: A new method of fabricating a convex charge coupled device is achieved. A silicon oxide layer is formed over the surface of a silicon substrate and patterned with a charge coupled device (CCD) electrode mask to provide openings to the silicon substrate. Nitride spacers are formed on the sidewalls of the openings. The integrated circuit is coated with a spin-on-glass layer. After curing, the spin-on-glass layer is etched back to expose the nitride spacers. Removing the nitride spacers leaves a second set of openings to the silicon substrate. Ions are implanted into the substrate through the second set of openings. The oxide layer is removed. The wafer is globally oxidized resulting in a thermal oxide layer with undulatory thickness. The thermal oxide is removed leaving a convex surface on the silicon substrate. A gate oxide layer is formed on the convex surface of the silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form gate electrodes to complete formation of the charge coupled device.

Abstract translation: 实现了一种制造凸电荷耦合器件的新方法。 在硅衬底的表面上形成硅氧化物层，并用电荷耦合器件（CCD）电极掩模构图，以向硅衬底提供开口。 氮化物间隔物形成在开口的侧壁上。 集成电路涂有旋涂玻璃层。 固化后，将旋涂玻璃层回蚀以暴露氮化物间隔物。 去除氮化物间隔物留下第二组开口到硅衬底。 离子通过第二组开口植入衬底。 去除氧化物层。 晶片被全局氧化，导致具有波浪厚度的热氧化层。 去除热氧化物，留下硅衬底上的凸表面。 在硅衬底的凸表面上形成栅氧化层。 沉积覆盖栅极氧化物层的多晶硅层并图案化以形成栅电极以完成电荷耦合器件的形成。

公开(公告)号：US6030892A

公开(公告)日：2000-02-29

申请号：US866131

申请日：1997-05-30

Applicant: Kun-Lin Wu ,  Hao-Kuang Chiu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Kun-Lin Wu ,  Hao-Kuang Chiu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/3105 ,  H01L21/4763

CPC classification number: H01L21/31053

Abstract: A method of preventing overpolishing in a chemical-mechanical polishing operation includes using a spin-on polymer material instead of spin-on glass as the local planarization material. The spin-on polymer layer is further used as a polishing stop layer so as to prevent damage to components due to overpolishing, because the polishing rate of the spin-on polymer layer in a chemical-mechanical polishing operation is, in general, lower than the polishing rate of the silicon dioxide layer formed using plasma enhanced chemical vapor deposition.

Abstract translation: 在化学机械抛光操作中防止过度抛光的方法包括使用旋涂聚合物材料代替旋涂玻璃作为局部平坦化材料。 旋涂聚合物层进一步用作抛光停止层，以防止由于过度抛光而损坏组分，因为化学机械抛光操作中的旋涂聚合物层的抛光速率通常低于 使用等离子体增强化学气相沉积形成的二氧化硅层的抛光速率。

公开(公告)号：US06225222B1

公开(公告)日：2001-05-01

申请号：US09219490

申请日：1998-12-23

Applicant: Chi-Cheng Yang ,  Kuo-Yun Kuo ,  Jenn-Tarng Lin

Inventor： Chi-Cheng Yang ,  Kuo-Yun Kuo ,  Jenn-Tarng Lin

IPC: H01L2144

CPC classification number: H01L21/76856 ,  H01L21/76843 ,  H01L21/76855

Abstract: Methods for enhancing the effectiveness of barrier layers, needed to prevent interaction between overlying aluminum interconnect metallizations, and underlying silicon device regions, has been developed. One method consists of using dual layers of titanium nitride, on titanium disilicide. The first titanium nitride layer is obtained via rapid thermal annealing of an underlying titanium layer, in a nitrogen containing ambient, also resulting in the formation of the underlying titanium disilicide layer. The second titanium nitride layer is deposited using reactive sputtering. A second method, used to create an enhanced barrier layer, is to reactively sputter titanium nitride, directly on an underlying titanium layer. Rapid thermal annealing, in an ammonia and oxygen ambient, results in an oxygen containing titanium nitride barrier layer. The rapid thermal anneal cycle also converts the underlying titanium layer, to the desired titanium disilicide layer. The barriers produced by these methods have demonstrated barrier effectiveness, in terms of preventing aluminum penetration, when compared to counterparts, fabricated without the use of the processes, described in this invention.

Abstract translation: 已经开发了用于增强防止层的有效性的方法，以防止上覆铝互连金属化之间的相互作用以及下面的硅器件区域。 一种方法包括在二硅化钛上使用双层氮化钛。 第一氮化钛层通过在含氮环境中的下层钛层的快速热退火获得，也导致下面的二硅化钛层的形成。 使用反应溅射沉积第二氮化钛层。 用于产生增强的阻挡层的第二种方法是直接在下层钛层上反应溅射氮化钛。 在氨和氧环境中的快速热退火导致含氧氮化钛阻挡层。 快速热退火循环还将下面的钛层转化为所需的二硅化钛层。 通过这些方法产生的障碍已经证明了与不使用本发明描述的方法制造的对比物相比，防止铝渗透的屏障效能。

公开(公告)号：US6048788A

公开(公告)日：2000-04-11

申请号：US9333

申请日：1998-01-20

Applicant: Hung-Yi Huang ,  Wen-Yi Hsieh ,  Chi-Rong Lin ,  Jenn-Tarng Lin

Inventor： Hung-Yi Huang ,  Wen-Yi Hsieh ,  Chi-Rong Lin ,  Jenn-Tarng Lin

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76862 ,  H01L21/76843 ,  H01L21/76856

Abstract: A method of forming a metal plug. A contact window is formed to penetrate through a dielectric layer on a substrate having a MOS formed thereon. A titanium glue layer is formed on the dielectric layer and the circumference of the contact window. A titanium barrier layer is formed on the titanium nitride layer. Using nitrogen plasma bombardment on the titanium nitride layer, the structure of the titanium nitride layer is transformed. The number of the nucleation seeds is increased, and the size of grains is reduced. A metal layer is formed on the titanium nitride layer and fills the contact window. A part of the metal layer is removed and a metal plug within the contact window is formed.

Abstract translation: 一种形成金属塞的方法。 形成接触窗口，以穿透其上形成有MOS的基板上的电介质层。 在介电层和接触窗的圆周上形成钛胶层。 在氮化钛层上形成钛阻挡层。 在氮化钛层上使用氮等离子体轰击，转变了氮化钛层的结构。 成核种子的数量增加，晶粒尺寸减小。 在氮化钛层上形成金属层，并填充接触窗。 去除金属层的一部分并形成接触窗内的金属塞。

公开(公告)号：US5883004A

公开(公告)日：1999-03-16

申请号：US920172

申请日：1997-08-25

Applicant: Hao-Kuang Shiu ,  Kun-Lin Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Hao-Kuang Shiu ,  Kun-Lin Wu ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31053 ,  H01L21/76819

Abstract: A method for planarizing interlayer dielectric is disclosed. The present invention includes firstly forming a barrier layer over a semiconductor substrate. Next, a buffer layer is formed on the barrier layer by a spin-on-glass technique. A dielectric layer is formed on the buffer layer, wherein etch rate of the dielectric layer is larger than etch rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the dielectric layer. Finally, the dielectric layer is etched back using the buffer layer as buffer, thereby planarizing the dielectric layer.

Abstract translation: 公开了一种平面化层间电介质的方法。 本发明包括首先在半导体衬底上形成阻挡层。 接下来，通过旋涂玻璃技术在阻挡层上形成缓冲层。 在缓冲层上形成电介质层，其中介电层的蚀刻速率大于缓冲层的蚀刻速率，势垒层用作来自电介质层的自掺杂块。 最后，使用缓冲层作为缓冲层来回蚀介电层，从而平坦化介电层。

公开(公告)号：US5990004A

公开(公告)日：1999-11-23

申请号：US115944

申请日：1998-07-15

Applicant: Yu-Ru Yang ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Yu-Ru Yang ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/28568 ,  H01L21/76877

Abstract: A method for forming a barrier layer inside a contact in a semiconductor wafer is disclosed herein. The forgoing semiconductor wafer includes a dielectric layer on a silicon contained layer. A portion of the silicon contained layer is exposed by the contact. The method mentioned above includes the following steps.First, form a conductive layer on the topography of the semiconductor wafer by a method other than CVD to increase the ohmic contact to the exposed silicon contained layer. Thus a first portion of the conductive layer is formed on the dielectric layer, and a second portion of the conductive layer is formed on the exposed silicon contained layer. Next, remove the first portion of the conductive layer to expose the dielectric layer. Finally, use a chemical vapor deposition (CVD) method to form the barrier layer on the dielectric layer and the first portion of the conductive layer to prevent said silicon contained layer from exposure.

Abstract translation: 本文公开了一种在半导体晶片的接触部内形成阻挡层的方法。 前述的半导体晶片包括在含硅层上的电介质层。 含硅层的一部分被接触露出。 上述方法包括以下步骤。 首先，通过CVD以外的方法在半导体晶片的形貌上形成导电层，以增加暴露的含硅层的欧姆接触。 因此，导电层的第一部分形成在电介质层上，导电层的第二部分形成在暴露的硅含量层上。 接下来，去除导电层的第一部分以暴露电介质层。 最后，使用化学气相沉积（CVD）方法在电介质层和导电层的第一部分上形成阻挡层，以防止所述含硅层暴露。

公开(公告)号：US5883014A

公开(公告)日：1999-03-16

申请号：US968746

申请日：1997-08-05

Applicant: Shiaw-Rong Chen ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Shiaw-Rong Chen ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: H01L21/30 ,  H01L21/316 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/3003 ,  H01L21/316 ,  H01L21/76826

Abstract: A method for treating via sidewalls comprising the steps of providing a substrate having a number of metallic wires already formed; depositing a liner oxide layer; depositing an organic spin-on-glass layer; and depositing a second oxide layer. The second oxide layer is planarized by a chemical-mechanical polishing method. Photolithographic and etching methods, employing oxygen plasma treatment as well as a wet etching removal method are used to form vias above the metallic layers. A hydrogen plasma treatment is performed for the via sidewalls to prevent the occurrence of out-gassing and to obtain superior electrical properties. A titanium/titanium nitride film is deposited, and aluminium or tungsten is deposited into the vias and to form aluminium or tungsten plugs, thus completing the manufacturing process according to this invention. A semiconductor device formned by this method is also described.

Abstract translation: 一种用于处理通孔侧壁的方法，包括以下步骤：提供具有已经形成的多个金属线的基底; 沉积衬里氧化物层; 沉积有机旋涂玻璃层; 和沉积第二氧化物层。 通过化学机械抛光方法对第二氧化物层进行平面化。 使用氧等离子体处理的光刻和蚀刻方法以及湿蚀刻去除方法来在金属层上方形成通孔。 对通孔侧壁进行氢等离子体处理，以防止排气的发生并获得优异的电气性能。 沉积钛/氮化钛膜，并将铝或钨沉积到通孔中并形成铝或钨插塞，从而完成根据本发明的制造过程。 还描述了通过该方法形成的半导体器件。

公开(公告)号：US5876508A

公开(公告)日：1999-03-02

申请号：US818898

申请日：1997-03-17

Applicant: Kun-Lin Wu ,  Chien-Hsien Lai ,  Horng-Bor Lu ,  Jenn-Tarng Lin

Inventor： Kun-Lin Wu ,  Chien-Hsien Lai ,  Horng-Bor Lu ,  Jenn-Tarng Lin

IPC: B08B3/02 ,  B24B37/04 ,  B24B53/007 ,  C11D3/39 ,  C11D7/06 ,  C11D7/08 ,  H01L21/306 ,  C03C25/00 ,  C23G1/02

CPC classification number: H01L21/02052 ,  B08B3/02 ,  B24B37/04 ,  B24B53/017 ,  C11D3/3947 ,  C11D7/06 ,  C11D7/08 ,  H01L21/30625 ,  Y10S438/959

Abstract: A method for effectively cleaning the slurry remnants left on a polishing pad after the completion of a chemical mechanical polish (CMP) process is provided. This method is able to substantially thoroughly clean away all of the slurry remnants left on the polishing pad. In the method of the invention, the first step is to prepare a cleaning agent which is a mixture of H.sub.2 O.sub.2, deionized water, an acid solution, and an alkaline solution mixed to a predetermined ratio. The cleaning agent is subsequently directed to a nozzle formed in the pad dresser. This allows the cleaning agent to be jetted forcibly onto the slurry remnants on the polishing pad so as to clean the slurry remnants away from the polishing pad. The cleaning agent can be provided with predetermined ratios for various kinds of slurries so that the cleaning agent can be adjusted to be either acid or alkaline in nature. This can allow an increase in the repellent force between the particles of the slurry remnants and the underlying polishing pad that is caused by the so-called zeta potential, thus allowing the slurry remnants to be more easily removed from the polishing pad.

Abstract translation: 提供了在完成化学机械抛光（CMP）工艺之后有效地清洁留在抛光垫上的浆料残余物的方法。 该方法能够基本上彻底地清除留在抛光垫上的所有浆料残余物。 在本发明的方法中，第一步是制备一种清洗剂，它是以预定比例混合的H 2 O 2，去离子水，酸性溶液和碱性溶液的混合物。 随后将清洁剂引导到形成在修整器中的喷嘴。 这样可以将洗涤剂强制地喷射到抛光垫上的浆料残余物上，以清除离开抛光垫的浆料残余物。 可以为各种浆料提供预定比例的清洗剂，使清洗剂本质上可以调节为酸性或碱性。 这可以增加由所谓的ζ电位引起的浆料残留物的颗粒和下面的抛光垫之间的驱除力，从而使浆料残余物更容易从抛光垫上去除。