公开(公告)号：US08120100B2

公开(公告)日：2012-02-21

申请号：US12616770

申请日：2009-11-11

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

IPC: H01L27/108 ,  H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

Abstract: An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.

Abstract translation: 重叠沟槽栅极半导体器件包括半导体衬底，设置在半导体衬底上的多个浅沟槽，设置在浅沟槽中的第一导电层，分别设置在每个浅沟槽中的多个深沟槽，设置在第二导电层中的第二导电层 深沟槽，源极金属层和栅极金属层。 每个深沟槽在每个浅沟槽下延伸到半导体衬底中。 源极金属层电连接到第二导电层，并且栅极金属层电连接到第一导电层。

公开(公告)号：US08680609B2

公开(公告)日：2014-03-25

申请号：US13091160

申请日：2011-04-21

Applicant: Wei-Chieh Lin ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Jia-Fu Lin

IPC: H01L29/76

CPC classification number: H01L29/7828 ,  H01L21/26586 ,  H01L29/41766 ,  H01L29/66666

Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.

Abstract translation: 耗尽型沟槽半导体器件的制造方法包括以下步骤。 首先，提供包括设置在其上的漂移外延层的衬底。 沟槽设置在漂移外延层中。 栅极电介质层形成在沟槽的内侧壁和漂移外延层的上表面上。 基极掺杂区域形成在漂移外延层中并与沟槽的一侧相邻。 形成薄的掺杂区域并保形地接触栅极电介质层。 形成栅极材料层以填充沟槽。 源极掺杂区域形成在基极掺杂区域中，并且源极掺杂区域与沟槽侧面的薄掺杂区域重叠。 最后，形成接触掺杂区域以与薄掺杂区域重叠，并且接触掺杂区域与源极掺杂区域相邻。

公开(公告)号：US08319284B2

公开(公告)日：2012-11-27

申请号：US12839426

申请日：2010-07-20

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jia-Fu Lin ,  Po-Hsien Li

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jia-Fu Lin ,  Po-Hsien Li

IPC: H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0657 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7816 ,  H01L29/7835

Abstract: A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.

Abstract translation: 横向扩散的金属氧化物半导体器件包括衬底，栅极电介质层，栅极多晶硅层，源极区域，漏极区域，体区域，第一漏极接触插塞，源极多晶硅层，绝缘层， 和源极金属层。 设置在漏极区域上的栅极电介质层上的源极多晶硅层可以用作场板，以增强击穿电压并增加漏极 - 源极电容。 此外，本发明的第一漏极接触插塞可以减小漏极 - 源极导通电阻和水平延长长度。

公开(公告)号：US20120139037A1

公开(公告)日：2012-06-07

申请号：US13091160

申请日：2011-04-21

Applicant: Wei-Chieh Lin ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Jia-Fu Lin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7828 ,  H01L21/26586 ,  H01L29/41766 ,  H01L29/66666

Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.

Abstract translation: 耗尽型沟槽半导体器件的制造方法包括以下步骤。 首先，提供包括设置在其上的漂移外延层的衬底。 沟槽设置在漂移外延层中。 栅极电介质层形成在沟槽的内侧壁和漂移外延层的上表面上。 基极掺杂区域形成在漂移外延层中并与沟槽的一侧相邻。 形成薄的掺杂区域并保形地接触栅极电介质层。 形成栅极材料层以填充沟槽。 源极掺杂区域形成在基极掺杂区域中，并且源极掺杂区域与沟槽侧面的薄掺杂区域重叠。 最后，形成接触掺杂区域以与薄掺杂区域重叠，并且接触掺杂区域与源极掺杂区域相邻。

公开(公告)号：US20110084334A1

公开(公告)日：2011-04-14

申请号：US12615271

申请日：2009-11-10

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Jia-Fu Lin ,  Chia-Hui Chen

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Jia-Fu Lin ,  Chia-Hui Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734

Abstract: A bilateral conduction semiconductor device and a manufacturing method thereof are provided. The bilateral conduction semiconductor device includes an epitaxial layer having a first conductive type and a first trench, a first gate conductive layer disposed on a sidewall of the first trench, a second gate conductive layer disposed opposite to the first gate conductive layer, and a doped region having the first conductive type. The doped region is disposed in the epitaxial layer between the first gate conductive layer and the second gate conductive layer, and a doped concentration of the doped region is larger than a doped concentration of the epitaxial layer.

Abstract translation: 提供了一种双向传导半导体器件及其制造方法。 双向传导半导体器件包括具有第一导电类型和第一沟槽的外延层，设置在第一沟槽的侧壁上的第一栅极导电层，与第一栅极导电层相对设置的第二栅极导电层和掺杂 区域具有第一导电类型。 掺杂区域设置在第一栅极导电层和第二栅极导电层之间的外延层中，掺杂区域的掺杂浓度大于外延层的掺杂浓度。

公开(公告)号：US08178923B2

公开(公告)日：2012-05-15

申请号：US12840283

申请日：2010-07-20

Applicant: Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

Inventor： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

IPC: H01L23/48

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734

Abstract: A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

Abstract translation: 提供了具有低栅极输入电阻的功率半导体器件及其制造方法。 功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。 金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。 因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

公开(公告)号：US07012288B2

公开(公告)日：2006-03-14

申请号：US10267215

申请日：2002-10-08

Applicant: Chien Ping Lee ,  Hin Fai Chau ,  Nanlei Larry Wang ,  Clarence John Dunnrowicz ,  Yan Chen ,  Barry Jia-Fu Lin

Inventor： Chien Ping Lee ,  Hin Fai Chau ,  Nanlei Larry Wang ,  Clarence John Dunnrowicz ,  Yan Chen ,  Barry Jia-Fu Lin

IPC: H01L31/0336

CPC classification number: H01L29/7371 ,  H01L29/0821

Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

Abstract translation: 异质结双极晶体管（HBT）中的安全操作区域（SOA）通过在晶体管中提供集电极区域来改善，晶体管在基极区域和下面的子集电极区域之间具有渐变（均匀或阶梯状）掺杂，集电极掺杂较低 靠近基极并且在子集电极附近较高，并且集电极掺杂小于子集电极的掺杂。 当集电极电流增加时，非均匀掺杂的集电极会降低Kirk效应引起的击穿。