公开(公告)号：US08178923B2

公开(公告)日：2012-05-15

申请号：US12840283

申请日：2010-07-20

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

IPC分类号： H01L23/48

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734

摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

摘要翻译： 提供了具有低栅极输入电阻的功率半导体器件及其制造方法。 功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。 金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。 因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

公开(公告)号：US20110291183A1

公开(公告)日：2011-12-01

申请号：US12840283

申请日：2010-07-20

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734

摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

摘要翻译： 提供了具有低栅极输入电阻的功率半导体器件及其制造方法。 功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。 金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。 因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

公开(公告)号：US08362529B2

公开(公告)日：2013-01-29

申请号：US12784505

申请日：2010-05-21

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

IPC分类号： H01L29/76

CPC分类号： H01L27/06 ,  H01L29/739

摘要： A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.

摘要翻译： 具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域 设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层 。 第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

公开(公告)号：US20110215374A1

公开(公告)日：2011-09-08

申请号：US12784505

申请日：2010-05-21

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

IPC分类号： H01L27/06 ,  H01L29/739 ,  H01L21/336

CPC分类号： H01L27/06 ,  H01L29/739

摘要： A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.

摘要翻译： 具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域 设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层 。 第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

公开(公告)号：US08198684B2

公开(公告)日：2012-06-12

申请号：US12614434

申请日：2009-11-08

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0255 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

摘要翻译： 具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。 半导体衬底的上表面具有第一沟槽和第二沟槽。 沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。 沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

公开(公告)号：US20110084335A1

公开(公告)日：2011-04-14

申请号：US12614434

申请日：2009-11-08

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L23/60

CPC分类号： H01L27/0629 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0255 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

摘要翻译： 具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。 半导体衬底的上表面具有第一沟槽和第二沟槽。 沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。 沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

公开(公告)号：US20110062513A1

公开(公告)日：2011-03-17

申请号：US12616770

申请日：2009-11-11

申请人： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.

摘要翻译： 重叠沟槽栅极半导体器件包括半导体衬底，设置在半导体衬底上的多个浅沟槽，设置在浅沟槽中的第一导电层，分别设置在每个浅沟槽中的多个深沟槽，设置在第二导电层中的第二导电层 深沟槽，源极金属层和栅极金属层。 每个深沟槽在每个浅沟槽下延伸到半导体衬底中。 源极金属层电连接到第二导电层，并且栅极金属层电连接到第一导电层。

公开(公告)号：US08120100B2

公开(公告)日：2012-02-21

申请号：US12616770

申请日：2009-11-11

申请人： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.

摘要翻译： 重叠沟槽栅极半导体器件包括半导体衬底，设置在半导体衬底上的多个浅沟槽，设置在浅沟槽中的第一导电层，分别设置在每个浅沟槽中的多个深沟槽，设置在第二导电层中的第二导电层 深沟槽，源极金属层和栅极金属层。 每个深沟槽在每个浅沟槽下延伸到半导体衬底中。 源极金属层电连接到第二导电层，并且栅极金属层电连接到第一导电层。

公开(公告)号：US20110278671A1

公开(公告)日：2011-11-17

申请号：US12839426

申请日：2010-07-20

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jia-Fu Lin ,  Po-Hsien Li

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jia-Fu Lin ,  Po-Hsien Li

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7816 ,  H01L29/7835

摘要： A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.

摘要翻译： 横向扩散的金属氧化物半导体器件包括衬底，栅极电介质层，栅极多晶硅层，源极区域，漏极区域，体区域，第一漏极接触插塞，源极多晶硅层，绝缘层， 和源极金属层。 设置在漏极区域上的栅极电介质层上的源极多晶硅层可以用作场板，以增强击穿电压并增加漏极 - 源极电容。 此外，本发明的第一漏极接触插塞可以减小漏极 - 源极导通电阻和水平延长长度。

公开(公告)号：US08680609B2

公开(公告)日：2014-03-25

申请号：US13091160

申请日：2011-04-21

申请人： Wei-Chieh Lin ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Jia-Fu Lin

IPC分类号： H01L29/76

CPC分类号： H01L29/7828 ,  H01L21/26586 ,  H01L29/41766 ,  H01L29/66666

摘要： A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.

摘要翻译： 耗尽型沟槽半导体器件的制造方法包括以下步骤。 首先，提供包括设置在其上的漂移外延层的衬底。 沟槽设置在漂移外延层中。 栅极电介质层形成在沟槽的内侧壁和漂移外延层的上表面上。 基极掺杂区域形成在漂移外延层中并与沟槽的一侧相邻。 形成薄的掺杂区域并保形地接触栅极电介质层。 形成栅极材料层以填充沟槽。 源极掺杂区域形成在基极掺杂区域中，并且源极掺杂区域与沟槽侧面的薄掺杂区域重叠。 最后，形成接触掺杂区域以与薄掺杂区域重叠，并且接触掺杂区域与源极掺杂区域相邻。