公开(公告)号：US07233134B2

公开(公告)日：2007-06-19

申请号：US10846569

申请日：2004-05-17

Applicant: Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

Inventor： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

IPC: G05F1/40

CPC classification number: H02M3/158

Abstract: A DC-to-DC converter comprises a sense circuit to sense the output voltage of the converter to generate a feedback signal, a transconductive amplifier to amplify a difference between the feedback signal and a threshold signal to generate a first current and to generate a second current in response to a load transient, a charging circuit connected with the first current to generate a charging voltage, a driver to compare the charging voltage with two reference signals to generate a pair of low-side and high-side driving signals, and a fast response circuit to compare a load transient signal corresponding to the second current with a third reference signal to generate a bypass signal to drive the output stage of the converter in the load transient.

Abstract translation: DC-DC转换器包括用于感测转换器的输出电压以产生反馈信号的感测电路，用于放大反馈信号和阈值信号之间的差异的跨导放大器以产生第一电流并产生第二电流 响应于负载瞬变的电流，与第一电流连接以产生充电电压的充电电路，将充电电压与两个参考信号进行比较的驱动器，以产生一对低侧和高侧驱动信号，以及 快速响应电路，将与第二电流相对应的负载瞬态信号与第三参考信号进行比较，以产生旁路信号，以在负载瞬变中驱动转换器的输出级。

公开(公告)号：US07073047B2

公开(公告)日：2006-07-04

申请号：US10064454

申请日：2002-07-17

Applicant: Kuang-Kai Kuo ,  Kuo-Ping Liu

Inventor： Kuang-Kai Kuo ,  Kuo-Ping Liu

IPC: G06F12/00

CPC classification number: G06F13/1631

Abstract: A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of synchronous transmissions. On receiving a first section read address, the control chip operates to compare the first section read address with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, a second section read address is received and compared with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, permission for executing the memory read command is granted only after the memory-write command inside the memory-write command queue having an identical write address is executed.

公开(公告)号：US08525505B2

公开(公告)日：2013-09-03

申请号：US12766246

申请日：2010-04-23

Applicant: Ko-Cheng Wang ,  Kuo-Ping Liu ,  Chih-Wei Tseng

Inventor： Ko-Cheng Wang ,  Kuo-Ping Liu ,  Chih-Wei Tseng

IPC: G05F1/575

CPC classification number: H02M3/1588 ,  H02M1/14 ,  Y02B70/1466

Abstract: A PWM controller and control method for a DC-DC voltage converter filter the high-frequency component of the voltage at the phase node between high-side and low-side elements of the voltage converter to generate a signal synchronous and in phase or out-of-phase with the inductor current of the voltage converter, to achieve a low-ripple output voltage and stable loop control.

Abstract translation: 用于DC-DC电压转换器的PWM控制器和控制方法对电压转换器的高侧和低侧元件之间的相位节点处的电压的高频分量进行滤波，以产生同步和相位或相位的信号， 与电压转换器的电感电流相位，实现低纹波输出电压和稳定的环路控制。

公开(公告)号：US07023253B2

公开(公告)日：2006-04-04

申请号：US10882159

申请日：2004-07-02

Applicant: Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

Inventor： Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

IPC: H03K5/00

CPC classification number: H03F3/217 ,  H02M3/1588 ,  H03K7/08 ,  Y02B70/1466

Abstract: In a noise sensitivity improved switching system and method thereof, comprised sensing the output voltage of the switching system to generate a feedback signal, respectively amplifying the feedback signal by two gains to generate two signals in phase or out of phase, filtering one of the two amplified signals, and summing or comparing the filtered signal and the other one, thereby reducing the noise interference to the switching system.

Abstract translation: 在噪声敏感度改进的开关系统及其方法中，包括感测开关系统的输出电压以产生反馈信号，分别通过两个增益来放大反馈信号以产生相或异相的两个信号，滤波两个 放大信号，并对滤波后的信号进行求和或比较，从而降低对交换系统的噪声干扰。

公开(公告)号：US06946823B2

公开(公告)日：2005-09-20

申请号：US10846601

申请日：2004-05-17

Applicant: Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

Inventor： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

IPC: H02M3/158 ,  G05F1/575

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A delta-sigma DC-to-DC converter comprises a pair of high-side and low-side switches switched to convert an input voltage to an output voltage, a sense circuit to sense the output voltage of the converter to generate a feedback signal, a transconductive amplifier to amplify a difference between the feedback signal and a threshold signal to generate a differential current, a charging circuit connected with the differential current to generate a charging voltage, and a driver to compare the charging voltage with two reference signals to generate the pair of low-side and high-side driving signals.

Abstract translation: Δ-ΣDC-DC转换器包括一对开关将输入电压转换为输出电压的高侧和低侧开关，感测电路以感测转换器的输出电压以产生反馈信号， 用于放大反馈信号和阈值信号之间的差异以产生差分电流的跨导放大器，与差分电流连接以产生充电电压的充电电路，以及将充电电压与两个参考信号进行比较的驱动器，以产生 一对低侧和高侧驱动信号。

公开(公告)号：US06624661B2

公开(公告)日：2003-09-23

申请号：US10121586

申请日：2002-04-15

Applicant: Chi Chang ,  Kuo-Ping Liu

Inventor： Chi Chang ,  Kuo-Ping Liu

IPC: H03K190175

CPC classification number: H03K19/018585

Abstract: This specification discloses a programmable drive circuit for the I/O port. Using a logic circuit, the driver on the IC I/O port can be programmed to be an open-drained driver or a push-pull driver. In an embodiment of the invention, the programmable drive circuit contains a first transistor group and a second transistor group connected in series between a work voltage and a ground level. A first logic circuit controls the first transistor group, and a second logic circuit controls the second transistor group. The logic circuits are controlled by a select signal so that the first transistor group and the second transistor group become the open-drained driver or the push-pull driver.

Abstract translation: 本说明书公开了用于I / O端口的可编程驱动电路。 使用逻辑电路，IC I / O端口上的驱动程序可以编程为开放驱动的驱动程序或推挽式驱动程序。 在本发明的一个实施例中，可编程驱动电路包含在工作电压和地电平之间串联连接的第一晶体管组和第二晶体管组。 第一逻辑电路控制第一晶体管组，第二逻辑电路控制第二晶体管组。 逻辑电路由选择信号控制，使得第一晶体管组和第二晶体管组成为开路驱动器或推挽驱动器。

公开(公告)号：US06463013B1

公开(公告)日：2002-10-08

申请号：US09631293

申请日：2000-08-02

Applicant: Kuo-Ping Liu ,  Jiin Lai ,  Jyh-fong Lin ,  Yu-Wei Lin

Inventor： Kuo-Ping Liu ,  Jiin Lai ,  Jyh-fong Lin ,  Yu-Wei Lin

IPC: G04F500

CPC classification number: H03L7/199 ,  G06F1/06 ,  H03L7/07 ,  H03L7/23

Abstract: A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.

Abstract translation: 一种用于产生不同频率的时钟信号的时钟产生装置和方法。 时钟发生装置和方法接收和分割主时钟信号以获得参考时钟信号。 然后，参考时钟信号和第一反馈时钟信号被锁相以获得第一时钟信号。 此外，参考时钟信号和第二反馈时钟信号被锁相以获得第二时钟信号。 复位信号和第一时钟信号由分频器接收。 然后分频器输出第一反馈时钟信号。 另一分频器接收复位信号和第二时钟信号，然后输出第二反馈时钟信号。

公开(公告)号：US06400197B2

公开(公告)日：2002-06-04

申请号：US09766952

申请日：2001-01-22

Applicant: Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

Inventor： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

IPC: H03L700

CPC classification number: G06F5/06 ,  G06F1/10 ,  G06F2205/104 ,  H03L7/0814

Abstract: A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

Abstract translation: 一种具有用于校准延迟间隔的内部延迟锁定环路的信号延迟装置。 信号延迟装置接收输入信号，然后在预定义的延迟周期之后输出信号。 输入信号根据参考时钟信号而变化，所需的延迟周期是时钟信号的四分之一周期。 延迟装置包括多路复用器，反相器，相位检测器，计数器和延迟元件。 在校准期间，相位检测器，计数器和延迟元件形成可以自动设置延迟时间的延迟锁定环。

公开(公告)号：US06336198B1

公开(公告)日：2002-01-01

申请号：US09276652

申请日：1999-03-26

Applicant: Chung-Pang Yu ,  Kuo-Ping Liu ,  You-Ming Chiu

Inventor： Chung-Pang Yu ,  Kuo-Ping Liu ,  You-Ming Chiu

IPC: G01R3128

CPC classification number: G01R31/31926

Abstract: A chip testing system using an internal signal of the chip under test to produce a blanking signal so as to avoid a conflict in the turn-around cycle between input mode and output mode. The preceding signal, posterior signal and reverse phase signal of the output enable signal of the chip under test are used to match with a testing circuit for producing a blanking signal, which is driven only when the output enable signal is at a high potential, enabling the state machine in the chip to control data reading time, so as to avoid a conflict in the turn-around cycle between input mode and output mode.

Abstract translation: 使用被测芯片的内部信号的芯片测试系统产生消隐信号，以避免输入模式和输出模式之间的周转周期的冲突。 使用被测芯片的输出使能信号的前一信号，后信号和反相信号与用于产生消隐信号的测试电路相匹配，该消隐信号仅在输出使能信号处于高电位时被驱动，使得能够 芯片中的状态机控制数据读取时间，以避免在输入模式和输出模式之间的周转周期中发生冲突。