公开(公告)号：US09937536B2

公开(公告)日：2018-04-10

申请号：US13547275

申请日：2012-07-12

Applicant: Kuo-Yin Lin ,  Chih-I Peng ,  Kun-Tai Wu ,  Teng-Chun Tsai ,  Hsiang-Pi Chang ,  Cary Chia-Chiung Lo

Inventor： Kuo-Yin Lin ,  Chih-I Peng ,  Kun-Tai Wu ,  Teng-Chun Tsai ,  Hsiang-Pi Chang ,  Cary Chia-Chiung Lo

IPC: B08B9/093 ,  H01L21/67 ,  B24B37/34 ,  B08B5/02

CPC classification number: B08B9/093 ,  B08B5/02 ,  B24B37/34 ,  H01L21/67028

Abstract: Among other things, one or more techniques and/or systems are provided for cleaning a polishing module of a semiconductor polishing apparatus. Purge air flow can be supplied into the polishing module (e.g., directed towards a polishing unit, a shield, and/or other polishing components) to create turbulence air flow within the polishing module. An auxiliary exhaust can be invoked to exhaust one or more particulates removed from the polishing module by the turbulence air flow. A purge air flow cycle can be performed by cycling the purge air flow and the auxiliary exhaust between on and off states. One or more purge air flow cycles can be performed during a main air flow cycle where laminar air flow is supplied into the polishing module and exhausted using a main exhaust. In this way, one or more particulates can be cleaned from the polishing module.

公开(公告)号：US20140014136A1

公开(公告)日：2014-01-16

申请号：US13547275

申请日：2012-07-12

Applicant: Kuo-Yin Lin ,  Chih-I Peng ,  Kun-Tai Wu ,  Teng-Chun Tsai ,  Hsiang-Pi Chang ,  Cary Chia-Chiung Lo

Inventor： Kuo-Yin Lin ,  Chih-I Peng ,  Kun-Tai Wu ,  Teng-Chun Tsai ,  Hsiang-Pi Chang ,  Cary Chia-Chiung Lo

IPC: B08B9/093

CPC classification number: B08B9/093 ,  B08B5/02 ,  B24B37/34 ,  H01L21/67028

Abstract: Among other things, one or more techniques and/or systems are provided for cleaning a polishing module of a semiconductor polishing apparatus. Purge air flow can be supplied into the polishing module (e.g., directed towards a polishing unit, a shield, and/or other polishing components) to create turbulence air flow within the polishing module. An auxiliary exhaust can be invoked to exhaust one or more particulates removed from the polishing module by the turbulence air flow. A purge air flow cycle can be performed by cycling the purge air flow and the auxiliary exhaust between on and off states. One or more purge air flow cycles can be performed during a main air flow cycle where laminar air flow is supplied into the polishing module and exhausted using a main exhaust. In this way, one or more particulates can be cleaned from the polishing module.

Abstract translation: 除其他之外，还提供了一种或多种技术和/或系统来清洁半导体抛光装置的抛光模块。 吹扫空气流可以被提供到抛光模块中（例如，指向抛光单元，屏蔽件和/或​​其它抛光部件），以在抛光模块内产生湍流空气流。 可以调用辅助排气以排出通过湍流空气流从抛光模块移除的一个或多个颗粒。 吹扫空气流循环可以通过在打开和关闭状态之间循环吹扫空气流和辅助排气来进行。 在主空气流循环期间可以执行一个或多个吹扫空气流循环，其中层流气流被供应到抛光模块中并且使用主排气排出。 以这种方式，可以从抛光模块清洁一个或多个颗粒。

公开(公告)号：US20060278959A1

公开(公告)日：2006-12-14

申请号：US11149575

申请日：2005-06-10

Applicant: Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

Inventor： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

IPC: H01L23/58 ,  H01L21/38

CPC classification number: H01L21/76829 ,  H01L21/3003 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/76828

Abstract: A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

Abstract translation: 公开了一种用于减小半导体结构中的漏电流的方法。 一个或多个电介质层形成在半导体衬底上，其上构造有至少一个器件。 在电介质层上形成含氢层。 氮化硅钝化层覆盖电介质层和含氢层。 含氢层的氢原子被引入到电介质层中而不被氮化硅层阻挡，从而减少其中的漏电流。

公开(公告)号：US20050070041A1

公开(公告)日：2005-03-31

申请号：US10672778

申请日：2003-09-26

Applicant: Chih-Ta Wu ,  Kuo-Yin Lin ,  Chia-Shiung Tsai

Inventor： Chih-Ta Wu ,  Kuo-Yin Lin ,  Chia-Shiung Tsai

IPC: H01L21/00 ,  H01L21/314

CPC classification number: H01L21/0228 ,  C23C16/45527 ,  H01L21/3141

Abstract: An atomic layer deposition method for forming a microelectronic layer employs a reactor chamber pressure of greater than about 500 mtorr and more preferably from about 20 to about 50 torr. By employing a reactor chamber pressure within the foregoing range, the microelectronic layer is formed with an enhanced deposition rate while employing the atomic layer deposition method, due to a gas phase chemical vapor deposition component to the atomic layer deposition method.

Abstract translation: 用于形成微电子层的原子层沉积方法采用的反应器室压力大于约500mtorr，更优选为约20至约50托。 通过采用上述范围内的反应室压力，由于采用原子层沉积方法的气相化学气相沉积成分，由于采用原子层沉积法，所以微电子层以增加的沉积速率形成。