公开(公告)号：US20190244824A1

公开(公告)日：2019-08-08

申请号：US16154902

申请日：2018-10-09

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

发明人： Haifeng XU ,  Dawei SHI ,  Liman PENG ,  Wentao WANG ,  Lu YANG ,  Lei YAO ,  Jinfeng WANG ,  Lei YAN ,  Jinjin XUE ,  Lin HOU ,  Fang YAN ,  Xiaowen SI ,  Zhijin MAN ,  Yaoda HOU ,  Yi LI ,  Lizhen ZHAO ,  Lei WANG

IPC分类号： H01L21/30 ,  H01L27/12

CPC分类号： H01L21/3003 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/1288 ,  H01L27/3265

摘要： The present disclosure relates to an array substrate, a method for fabricating the same, a display panel, and a method for fabricating the same. The array substrate includes a substrate, an active layer on the substrate, a first insulating layer on the active layer, a gate electrode and a first electrode on the first insulating layer, wherein a projection of the first electrode on the substrate and a projection of the active layer on the substrate do not overlap, a third insulating layer on the first electrode, a projection of the third insulating layer on the substrate does not overlap with a projection of the active layer on the substrate, a second electrode on the third insulating layer, and a second insulating layer on the gate electrode and the second electrode.

公开(公告)号：US20180331206A1

公开(公告)日：2018-11-15

申请号：US15543726

申请日：2016-07-25

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Jian MIN ,  Xiaolong LI ,  Tao GAO ,  Liangjian LI ,  Zhengyin XU

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/30 ,  H01L29/36 ,  H01L29/786

CPC分类号： H01L29/66757 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02675 ,  H01L21/0272 ,  H01L21/0274 ,  H01L21/3003 ,  H01L27/1285 ,  H01L27/1288 ,  H01L29/36 ,  H01L29/78618 ,  H01L29/78675

摘要： The present application discloses a method of fabricating a polycrystalline silicon thin film transistor, the method including forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor; the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; and crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer in the second region and doped with a dopant of the second dopant layer in the first region during the step of crystallizing the amorphous silicon layer.

公开(公告)号：US10079288B2

公开(公告)日：2018-09-18

申请号：US15175694

申请日：2016-06-07

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC分类号： H01L29/49 ,  H01L29/40 ,  H01L29/16 ,  H01L29/24 ,  H01L21/30 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3065

CPC分类号： H01L29/4941 ,  H01L21/02271 ,  H01L21/02592 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3003 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/16 ,  H01L29/24 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66575

摘要： A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.

公开(公告)号：US20180226497A1

公开(公告)日：2018-08-09

申请号：US15928563

申请日：2018-03-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li

IPC分类号： H01L29/66 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/08

CPC分类号： H01L21/02645 ,  H01L21/02236 ,  H01L21/3003 ,  H01L21/3065 ,  H01L21/76202 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

摘要： Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

公开(公告)号：US20180175042A1

公开(公告)日：2018-06-21

申请号：US15700615

申请日：2017-09-11

申请人： SK hynix Inc.

发明人： Il-Sik JANG ,  Ji-Hwan PARK ,  Mi-Ri LEE ,  Bong-Seok JEON ,  Yong-Soo JOUNG ,  Sun-Hwan HWANG

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L21/321 ,  H01L21/3215 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/223

CPC分类号： H01L27/10852 ,  H01L21/2236 ,  H01L21/3003 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/3215 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/75

摘要： A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a hydrogen-containing top electrode over the transistor; and performing an annealing process for hydrogen passivation after the capacitor is formed.

公开(公告)号：US09780124B2

公开(公告)日：2017-10-03

申请号：US15221642

申请日：2016-07-28

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Yasuyuki Arai

IPC分类号： H01L27/12 ,  H01L27/32 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/30 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1333

CPC分类号： H01L27/124 ,  G02F1/133553 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  G02F2201/123 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02686 ,  H01L21/3003 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L27/3279 ,  H01L29/66537 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78678 ,  H01L29/78684 ,  H01L29/78696

摘要： An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

公开(公告)号：US20170256420A1

公开(公告)日：2017-09-07

申请号：US15268006

申请日：2016-09-16

申请人： ZING SEMICONDUCTOR CORPORATION

发明人： DEYUAN XIAO ,  RICHARD R. CHANG

IPC分类号： H01L21/322 ,  H01L21/02

CPC分类号： H01L21/3225 ,  H01L21/02005 ,  H01L21/3003

摘要： The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

公开(公告)号：US09755064B2

公开(公告)日：2017-09-05

申请号：US15048112

申请日：2016-02-19

申请人： Kabushiki Kaisha Toshiba

发明人： Teruyuki Ohashi ,  Yuichiro Mitani ,  Tatsuo Shimizu ,  Ryosuke Iijima

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66 ,  H01L21/30

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L21/3003 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×1020 cm−3 or more and a maximum concentration of hydrogen (H) in the region being 1×1019 cm−3 or less.

公开(公告)号：US20170243959A1

公开(公告)日：2017-08-24

申请号：US15588969

申请日：2017-05-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li

IPC分类号： H01L29/66 ,  H01L29/04 ,  H01L21/3065 ,  H01L29/08

CPC分类号： H01L21/02645 ,  H01L21/02236 ,  H01L21/3003 ,  H01L21/3065 ,  H01L21/76202 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

摘要： Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

公开(公告)号：US20170207223A1

公开(公告)日：2017-07-20

申请号：US15312759

申请日：2015-05-28

申请人： SONY CORPORATION

发明人： KATSUHISA KUGIMIYA ,  KENICHI MURATA ,  HITOSHI OKANO ,  SHIGETAKA MORI ,  HIROYUKI KAWASHIMA ,  TAKUMA MATSUNO

IPC分类号： H01L27/108

CPC分类号： H01L27/10847 ,  H01L21/3003 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/1462 ,  H01L27/14634

摘要： A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.