公开(公告)号：US20060265680A1

公开(公告)日：2006-11-23

申请号：US11437583

申请日：2006-05-19

Applicant: Louis Scheffer ,  Joel Phillips

Inventor： Louis Scheffer ,  Joel Phillips

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The expected geometric shape includes systematic variations, which can be determined based on the layout, and the expected random variations, which can be determined based on the lithographic process.

公开(公告)号：US20060265677A1

公开(公告)日：2006-11-23

申请号：US11437794

申请日：2006-05-19

Applicant: Louis Scheffer ,  Wolfgang Staud ,  Judy Huckabay

Inventor： Louis Scheffer ,  Wolfgang Staud ,  Judy Huckabay

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for performing extraction since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The extracted electrical parameters are checked for acceptability. If not acceptable, then the IC design can be modified to address any identified problems or desired improvements to the design.

Abstract translation: 公开了一种改进的方法，系统和计算机程序产品，用于提高IC设计的电参数的精度。 一旦制造和平版印刷过程效果被考虑，就按照打印布局的预期几何模型进行提取。 这提供了一种更精确的执行提取方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。 检查提取的电气参数是否可接受。 如果不能接受，则可以修改IC设计以解决任何已识别的问题或对设计的期望改进。

公开(公告)号：US20050246675A1

公开(公告)日：2005-11-03

申请号：US10836582

申请日：2004-05-01

Applicant: Louis Scheffer

Inventor： Louis Scheffer

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, 4) selecting a feature in the upper layout, 5) retrieving, from the density map, the geometry coverage of a sub-region below the feature, 6) determining a vertical deviation of the feature using the geometry coverage, 7) determining an alteration to the modification using the vertical deviation, 8) applying the alteration to the modification, and 9) repeating for all features. In some embodiments, the upper layout is designed using a library of pretabulated models, each model containing a modification to a feature calculated to produce a satisfactory feature on a wafer.

Abstract translation: 一种用于使用用于IC的下层的下部布局的信息来修改IC的上层布局的方法，所述方法包括：1）接收包含特征的上部布局和对特征的修改，2）产生密度图 下部布局具有下部布局的子区域的几何覆盖，4）在上部布局中选择特征，5）从密度图中检索特征下方的子区域的几何覆盖，6）确定 使用几何覆盖的特征的垂直偏差，7）使用垂直偏差确定对修改的改变，8）将修改应用于修改，以及9）针对所有特征重复。 在一些实施例中，使用预制模型库设计上部布局，每个模型包含被计算以在晶片上产生令人满意的特征的特征的修改。

公开(公告)号：US20050216877A1

公开(公告)日：2005-09-29

申请号：US11143361

申请日：2005-06-01

Applicant: Robert Pack ,  Louis Scheffer

Inventor： Robert Pack ,  Louis Scheffer

IPC: G03F9/00 ,  G06F17/50

CPC classification number: G03F1/68 ,  G03F1/36 ,  G03F1/78

Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Abstract translation: 一种用于产生光刻掩模的方法包括产生集成电路设计数据和使用来自集成电路设计数据的上下文信息来写入掩模。