公开(公告)号：US5347542A

公开(公告)日：1994-09-13

申请号：US723288

申请日：1991-06-28

申请人： Christopher N. Kurby ,  Donald R. Beyer ,  Anne P. Davies-Walsh ,  Kevin L. Fluharty ,  Matthew R. Miller

发明人： Christopher N. Kurby ,  Donald R. Beyer ,  Anne P. Davies-Walsh ,  Kevin L. Fluharty ,  Matthew R. Miller

IPC分类号： H04L7/04 ,  H04L27/00 ,  H04L25/49

CPC分类号： H04L27/0008 ,  H04L7/041 ,  H04L7/046

摘要： In a system where 2-level modulation and 4-level modulation of communication signals exist, an apparatus (107) demodulates either modulation scheme by demodulating (301) a received signal under the presumption that it is a 4-level signal, and if the received signal is detected (309) to be a 2-level signal, the signal is then demodulated (319) as a 2-level signal.

摘要翻译： 在存在通信信号的2电平调制和4电平调制的系统中，设备（107）在推定为4电平信号的情况下解调（301）接收信号来解调任一调制方案，并且如果 检测到接收信号（309）为2电平信号，然后将信号解调（319）作为2电平信号。

公开(公告)号：US08683583B2

公开(公告)日：2014-03-25

申请号：US12958668

申请日：2010-12-02

申请人： Matthew R. Miller ,  Kenneth D. Johnson ,  Timothy William Burrell

发明人： Matthew R. Miller ,  Kenneth D. Johnson ,  Timothy William Burrell

IPC分类号： G06F21/00

CPC分类号： G06F21/6218 ,  G06F2221/2143

摘要： The subject disclosure is directed towards preventing the exploitation by malicious code of object state corruption vulnerabilities, such as use-after-free vulnerabilities. An object class is configured with a secret cookie in a virtual function table of the object, e.g., inserted at compile time. An instrumentation check inserted in the program code evaluates the secret cookie to determine whether the object state has been corrupted before object access (e.g., a call to one of the object's methods) is allowed. If corrupted, access to the object is prevented by the instrumentation check. Another instrumentation check may be used to determine whether the object's virtual table pointer points to a location outside of the module that contains the legitimate virtual function table; if so, object access is prevented.

摘要翻译： 该主题披露旨在防止恶意代码利用对象状态破坏漏洞（例如使用后免费漏洞）。 对象类在对象的虚拟功能表中配置有秘密cookie，例如在编译时插入。 插入程序代码中的检测检查将评估秘密cookie，以确定对象状态是否在对象访问之前已被破坏（例如，对对象的方法之一的调用）。 如果损坏，仪器检查会阻止对对象的访问。 可以使用另一种仪器检查来确定对象的虚拟表指针是否指向包含合法虚拟功能表的模块之外的位置; 如果是这样，则可以防止对象访问。

公开(公告)号：US07956781B2

公开(公告)日：2011-06-07

申请号：US12445029

申请日：2006-10-13

申请人： Omid Oliaei ,  Alan Bannon ,  Anthony Dunne ,  Matthew R. Miller ,  Daniel O'Hare

发明人： Omid Oliaei ,  Alan Bannon ,  Anthony Dunne ,  Matthew R. Miller ,  Daniel O'Hare

IPC分类号： H03M3/00

CPC分类号： H03M3/392 ,  H03M3/40

摘要： An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.

摘要翻译： 模数转换器装置包括耦合到第二积分器的第一积分器。 第一和第二积分器耦合以提供复极。 第一积分器选择性地与第二积分器电可去耦，从而去除复极。

公开(公告)号：US06930554B2

公开(公告)日：2005-08-16

申请号：US10623047

申请日：2003-07-18

申请人： Jyoti Mondal ,  Neil L. Calanca ,  Matthew R. Miller

发明人： Jyoti Mondal ,  Neil L. Calanca ,  Matthew R. Miller

IPC分类号： H03F1/22 ,  H03F3/45 ,  H03G3/30 ,  H03G3/10

CPC分类号： H03F1/223 ,  H03F1/22 ,  H03F3/45089 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/411 ,  H03F2203/45481 ,  H03G3/3052 ,  H03G3/3057

摘要： A variable gain control amplifier (10) and method provides a substantially constant input impedance and output impedance, and provides a substantially constant noise figure and third order harmonic. The variable gain control amplifier (10) includes an amplifier stage including at least a first intermediate fixed gain stage (22) operative to produce a first intermediate signal (30) in response to the input signal (20). The variable gain control amplifier (10) further includes at least a second intermediate fixed gain stage (24) operative to produce an output signal (18) in response to the first intermediate signal (30). A feedback circuit (16) is operative to produce a gain control signal (32) in response to the output signal (18). A gain control circuit (26) is coupled to the at least first intermediate fixed gain stage (22) and the second intermediate fixed gain stage (24), and receives the gain control signal (32) to control an amplitude of the intermediate signal (30).

摘要翻译： 可变增益控制放大器（10）和方法提供基本恒定的输入阻抗和输出阻抗，并且提供基本上恒定的噪声系数和三阶谐波。 可变增益控制放大器（10）包括放大器级，至少包括第一中间固定增益级（22），用于响应输入信号（20）产生第一中间信号（30）。 可变增益控制放大器（10）还包括至少第二中间固定增益级（24），其响应于第一中间信号（30）而产生输出信号（18）。 反馈电路（16）用于响应于输出信号（18）产生增益控制信号（32）。 增益控制电路（26）耦合到至少第一中间固定增益级（22）和第二中间固定增益级（24），并且接收增益控制信号（32）以控制中间信号 30）。

公开(公告)号：US06750704B1

公开(公告)日：2004-06-15

申请号：US10340335

申请日：2003-01-09

申请人： Lawrence Edwin Connell ,  Craig S. Petrie ,  Matthew R. Miller

发明人： Lawrence Edwin Connell ,  Craig S. Petrie ,  Matthew R. Miller

IPC分类号： H03F102

CPC分类号： H03F3/45753 ,  H03F2200/331

摘要： A differential amplifier comprises a differential input stage including first and second input devices and has first and second input electrodes and first and second output terminals. A differential load stage includes first and second load devices having first and second control electrodes respectively. The load stage is coupled to the differential input stage and to the first and second output terminals. First and second separate capacitive biasing networks are coupled to the first and second output terminals and respectively to the first and second control electrodes. During an offset-cancellation phase, the input electrodes are coupled to a common voltage. During an amplification phase, a differential input signal is applied to the input electrodes.

摘要翻译： 差分放大器包括具有第一和第二输入装置的差分输入级，并具有第一和第二输入电极以及第一和第二输出端子。 差分负载级包括分别具有第一和第二控制电极的第一和第二负载装置。 负载级耦合到差分输入级以及第一和第二输出端。 第一和第二分离电容偏置网络耦合到第一和第二输出端子，并分别耦合到第一和第二控制电极。 在偏移消除阶段期间，输入电极耦合到公共电压。 在放大阶段期间，差分输入信号被施加到输入电极。

公开(公告)号：US5521941A

公开(公告)日：1996-05-28

申请号：US620601

申请日：1990-11-29

申请人： David G. Wiatrowski ,  Matthew R. Miller ,  Christopher N. Kurby

发明人： David G. Wiatrowski ,  Matthew R. Miller ,  Christopher N. Kurby

IPC分类号： H04L25/06

CPC分类号： H04L25/062 ,  H04L25/066 ,  Y10T307/664

摘要： Symbol recovery for multi-level digital signals has traditionally been difficult because of the nature of the eye pattern output by the discriminator (103), and especially its response to a noisy or impeded signal environment. This method and apparatus for recovery thresholds adjusts (411 and 417) to the current state of the discriminator (103) output of the received signal, based on an attenuated (301) version of that signal. Using a fast adjust mode and slow adjust mode, the threshold generating circuitry (331 and 361) adapts to the signal based on data from the received signal fed into lock detectors (329 and 359) which determine the mode to use.

摘要翻译： 传统上由于鉴别器（103）输出的眼图的性质，特别是其对噪声或阻碍的信号环境的响应，多级数字信号的符号恢复是困难的。 该恢复阈值的方法和装置基于该信号的衰减（301）版本，调整（411和417）到接收信号的鉴别器（103）输出的当前状态。 使用快速调整模式和慢速调整模式，阈值产生电路（331和361）根据来自确定使用模式的锁定检测器（329和359）的接收信号的数据适应信号。

公开(公告)号：US20120265947A1

公开(公告)日：2012-10-18

申请号：US13086936

申请日：2011-04-14

申请人： Gregory J. Colombo ,  Hari Pulapaka ,  Arun U. Kishan ,  Stephen L. Hufnagel ,  Garrett Trent Leischner ,  Evan Lincoln Tice ,  Matthew R. Miller

发明人： Gregory J. Colombo ,  Hari Pulapaka ,  Arun U. Kishan ,  Stephen L. Hufnagel ,  Garrett Trent Leischner ,  Evan Lincoln Tice ,  Matthew R. Miller

IPC分类号： G06F12/00

CPC分类号： G06F3/0631 ,  G06F3/0671 ,  G06F9/5016 ,  G06F12/0223

摘要： In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

摘要翻译： 响应于从应用线程接收到的存储器分配请求，获得随机数（例如，从先前填充有多个随机数的随机数列表）。 基于随机数来确定与包括存储器的多个块的区域相关联的位图的至少一部分中的起始位置。 从起始位置开始扫描位图的一部分，以识别与多个块的可用块对应的位图中的位置，并将该可用块的指示返回给应用程序线程。

公开(公告)号：US5182761A

公开(公告)日：1993-01-26

申请号：US649083

申请日：1991-01-31

申请人： Donald R. Beyer ,  Matthew R. Miller ,  Krsman Martinovich

发明人： Donald R. Beyer ,  Matthew R. Miller ,  Krsman Martinovich

IPC分类号： H03D3/02 ,  H03L7/107 ,  H04L7/033 ,  H04L7/08 ,  H04L7/10

CPC分类号： H04L7/0331 ,  H04L7/08 ,  H04L7/10

摘要： A data transmission system receiver is disclosed which receives a formatted data stream (302) and operates in one of at least a first bandwidth mode and a second bandwidth mode. The formatted data stream (302) comprises a plurality of data edges (108, 110) and is sampled by a first clock signal (320). A plurality of clock edges (102, 104) defining transitions from one logic state to another is used to define "early" and "late" data edge occurrences. These occurrences are accumulated in accumulators (310, 312) and used as inputs to a clock counter (318) which produces a phase-adjusted clock signal (320). Additionally, the data transmission receiver comprises a detector (330) for detecting when a limited data stream (306) is synchronized with the phase-adjusted clock signal (320) and, in accordance with a predetermined algorithm, is able to switch the phase-lock circuit from the first bandwidth mode to the second bandwidth mode.

摘要翻译： 公开了一种数据传输系统接收机，其接收格式化的数据流（302）并且以至少第一带宽模式和第二带宽模式之一进行操作。 格式化数据流（302）包括多个数据边缘（108,110），并由第一时钟信号（320）进行采样。 使用定义从一个逻辑状态到另一逻辑状态的转换的多个时钟边缘（102,104）来定义“早期”和“晚期”数据边缘出现。 这些事件被累积在累加器（310,312）中，并用作产生相位调整时钟信号（320）的时钟计数器（318）的输入。 另外，数据传输接收机包括检测器（330），用于检测有限数据流（306）何时与相位调整时钟信号（320）同步，并且根据预定算法，能够切换相位调制信号 锁定电路从第一带宽模式到第二带宽模式。

公开(公告)号：US20090261902A1

公开(公告)日：2009-10-22

申请号：US12104874

申请日：2008-04-17

申请人： Pallab Midya ,  Matthew R. Miller ,  Theresa Paulo ,  William J. Roeckner

发明人： Pallab Midya ,  Matthew R. Miller ,  Theresa Paulo ,  William J. Roeckner

IPC分类号： H03F3/217

CPC分类号： H03F3/217

摘要： A circuit (104, 106) includes a comparison circuit (202, 504, 506, 602) and a correction circuit (204, 508, 510, 604). The comparison circuit provides a comparison signal (212, 524, 526, 612) in response to an error value (210, 520, 522, 610) and a reference value (214). The error value is based on a pulse modulated input signal (114) and a pulse modulated output signal (118). The correction circuit asynchronously provides a corrected pulse modulated signal (116) by selectively delaying and advancing an edge of the pulse modulated input signal based on the comparison signal. The pulse modulated output signal is based on the corrected pulse modulated signal.

摘要翻译： 电路（104,106）包括比较电路（202,504,506,602）和校正电路（204,508,510,604）。 比较电路响应于错误值（210,520,522,610）和参考值（214）提供比较信号（212,524,526,612）。 误差值基于脉冲调制输入信号（114）和脉冲调制输出信号（118）。 校正电路通过基于比较信号选择性地延迟和前进脉冲调制输入信号的边沿来异步地提供校正的脉冲调制信号（116）。 脉冲调制输出信号基于经校正的脉冲调制信号。

公开(公告)号：US07352311B2

公开(公告)日：2008-04-01

申请号：US11507919

申请日：2006-08-22

申请人： Matthew R. Miller ,  Pallab Midya ,  Poojan A. Wagh

发明人： Matthew R. Miller ,  Pallab Midya ,  Poojan A. Wagh

IPC分类号： H03M3/00

CPC分类号： H03M3/432

摘要： A system for a continuous time noise shaping analog-to-digital converter (“ADC”) with a suppressed carrier pulse width modulated (“PWM”) quantizer is disclosed. In particular, a suppressed carrier feedback signal may expand the dynamic range of a sigma delta modulated ADC and enhance the stability of the noise shaping loop.

摘要翻译： 公开了一种具有抑制载波脉宽调制（“PWM”）量化器的连续时间噪声整形模数转换器（“ADC”）的系统。 特别地，抑制的载波反馈信号可以扩展Σ-Δ调制ADC的动态范围，并增强噪声整形环路的稳定性。