公开(公告)号：US20240007126A1

公开(公告)日：2024-01-04

申请号：US18452458

申请日：2023-08-18

Applicant: Wacom Co., Ltd.

Inventor： Takeshi KOIKE

IPC: H03M3/00 ,  G06F3/038

CPC classification number: H03M3/40 ,  G06F3/038 ,  H03M3/344 ,  H03M3/43 ,  H03M3/464

Abstract: A delta-sigma modulation circuit is enabled to be used to detect a pen signal. An integrated circuit according to the present disclosure is a sensor controller that detects pen signals transmitted from an active pen. The integrated circuit includes a delta-sigma modulation circuit including a subtractor that subtracts a feedback signal from a received signal input from a sensor, an integrator that integrates an output signal of the subtractor, a quantizer that quantizes an output signal of the integrator, and a digital analog converter that generates the feedback signal based on an output value of the quantizer. The integrated circuit also has a processor that detects a level of the received signal based on an output value of the delta-sigma modulation circuit, and a gain controller that a level of the feedback signal based on the level of the received signal detected by the processor.

公开(公告)号：US20170170838A1

公开(公告)日：2017-06-15

申请号：US15366069

申请日：2016-12-01

Applicant: Syntropy Systems, LLC

Inventor： Christopher Pagnanelli

IPC: H03L7/191 ,  H03K19/21

CPC classification number: H03L7/191 ,  H03F1/08 ,  H03F1/30 ,  H03F1/3247 ,  H03F1/3258 ,  H03F3/2175 ,  H03F3/45475 ,  H03F2200/447 ,  H03F2203/45528 ,  H03K19/21 ,  H03M1/1038 ,  H03M1/785 ,  H03M3/358 ,  H03M3/40 ,  H03M3/402 ,  H03M3/502 ,  H03M7/3026 ,  H03M7/3033 ,  H04L7/0029 ,  H04L7/005 ,  H04L27/362

Abstract: An exemplary apparatus for converting fluctuations in periodicity of an input signal into proportional fluctuations in the amplitude of an output signal includes: an input line for accepting an input signal; a delay element with an input coupled to the input line and an output; a detector having a first input coupled to the input line, a second input coupled to the output of the delay element, and an output; an integrator having an input coupled to the output of the detector and an output; and an output line coupled to the output of the integrator. The delay element introduces a time delay which is greater than zero and less than twice the nominal oscillation period of the input signal. The detector performs a differencing operation. The integrator has a time constant of integration that is smaller than twice the delay applied by the delay element.

公开(公告)号：US20170134055A1

公开(公告)日：2017-05-11

申请号：US15318067

申请日：2014-06-23

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Mojtaba Ebrahimi ,  Mohamed Helaoui ,  Fadhel Ghannouchi ,  Fahimi Elsayed ,  Bradley John Morris

IPC: H04B1/04 ,  H04L27/26 ,  H03F3/24 ,  H03M7/30 ,  H03F3/19

CPC classification number: H04B1/0475 ,  H03F3/19 ,  H03F3/245 ,  H03F2200/331 ,  H03F2200/451 ,  H03M3/02 ,  H03M3/40 ,  H03M7/3015 ,  H03M7/302 ,  H04L27/2614

Abstract: Apparatuses and methods for power amplification and signal transmission using complex delta-sigma modulation are disclosed. In one embodiment, a complex delta sigma modulator unit comprising a complex polar quantizer within an integrator loop is disclosed. The complex polar quantizer quantizes the envelope of a complex integrated signal and produces a complex quantized output signal of substantially constant envelope. The complex quantized output signal is used in deriving a complex feedback signal within the integrator loop of the complex DSM. The complex quantized output signal may be used in driving a power amplifier substantially at saturation. In some embodiments, an adjacent channel power ratio (ACPR) enhancement technique is used to reduce the quantization noise in the complex quantized output signal.

公开(公告)号：US09112522B2

公开(公告)日：2015-08-18

申请号：US14319154

申请日：2014-06-30

Applicant: Enphase Energy, Inc.

Inventor： Michael Harrison

IPC: H03M3/00 ,  H03M3/02

CPC classification number: H03M3/02 ,  H03M3/40

Abstract: Embodiments of the present invention are directed to an analog to digital converter, comprising a comparator for comparing an analog input signal and an analog feedback signal output from a digital to analog converter to generate a digital direct output signal, a summer, coupled to the comparator, for summing the digital output signal with a digital feedback signal to generate a summed signal, a first integrator, coupled to the summer, for integrating the summed signal to generate a direct output signal and a second integrator, coupled to the first integrator and to the summer, for integrating the direct output signal to generate the digital feedback signal as a quadrature output signal.

Abstract translation: 本发明的实施例涉及一种模数转换器，包括比较器，用于比较模拟输入信号和从数模转换器输出的模拟反馈信号，以产生耦合到比较器的数字直接输出信号，加法器 用于将数字输出信号与数字反馈信号相加以产生加法信号，耦合到加法器的第一积分器，用于积分加和信号以产生直接输出信号和第二积分器，耦合到第一积分器，并耦合到第一积分器， 用于积分直接输出信号以产生数字反馈信号作为正交输出信号。

公开(公告)号：US08660170B1

公开(公告)日：2014-02-25

申请号：US13709036

申请日：2012-12-09

Applicant: Phuong Thu-Minh Huynh

Inventor： Phuong Thu-Minh Huynh

IPC: H04B3/46

CPC classification number: H03M3/38 ,  H03M3/37 ,  H03M3/40 ,  H03M3/41

Abstract: A calibration technique to compensate for the quadrature phase error between the in-phase and quadrature sampling clocks controlling the quadrature bandpass sampling delta-sigma analog-to-digital demodulator (QBS-ADD) is provided. A low-frequency test tone is injected in the feedback path, up-converted to the radio frequency (RF) frequency, and added to the input of the QBS-ADD. The test tone is demodulated by the QBS-ADD into an in-phase signal and a quadrature signal. The in-phase and quadrature signals are converted into the frequency domain by the discrete Fourier transform. The quadrature phase error is quantified based on the complex Fourier complex coefficients; and the phase difference between the in-phase and quadrature sampling clocks is corrected.

Abstract translation: 提供了一种用于补偿控制正交带通采样Δ-Σ模数转换器（QBS-ADD）的同相和正交采样时钟之间的正交相位误差的校准技术。 低频测试音被注入到反馈路径中，上变频到射频（RF）频率，并加到QBS-ADD的输入端。 测试音被QBS-ADD解调为同相信号和正交信号。 通过离散傅里叶变换将同相和正交信号转换成频域。 基于复傅立叶复数系数量化正交相位误差; 校正同相和正交采样时钟之间的相位差。

公开(公告)号：US20130083868A1

公开(公告)日：2013-04-04

申请号：US13249208

申请日：2011-09-29

Applicant: Péter Onódy

Inventor： Péter Onódy

IPC: H03M3/02 ,  H04L27/06

CPC classification number: H03M3/392 ,  H03M3/40 ,  H03M3/406 ,  H03M3/452

Abstract: A delta-sigma analog-to-digital converter (ADC) is disclosed. In one embodiment, the delta-sigma ADC includes a dual mode resonator and a plurality of switches. The delta-sigma ADC is configured to operate in a real modulation mode or a complex modulation mode based on settings of the plurality of switches.

Abstract translation: 公开了一种Δ-Σ模数转换器（ADC）。 在一个实施例中，Δ-ΣADC包括双模谐振器和多个开关。 Δ-ΣADC被配置为基于多个开关的设置以实际调制模式或复调制模式操作。

公开(公告)号：US08378870B1

公开(公告)日：2013-02-19

申请号：US13227268

申请日：2011-09-07

Applicant: Toru Matsuura

Inventor： Toru Matsuura

IPC: H03M1/66

CPC classification number: H03M1/0665 ,  H03M1/74 ,  H03M3/40 ,  H03M3/41 ,  H03M3/502

Abstract: The present invention provides a DAC (Digital to Analog Converter) capable of generating a transfer function having a notch for reducing an error signal level in a desired frequency band.The DAC of the present invention includes a switch bank to which at least two reference signals are inputted and which selects any of these signals and outputs the selected signal through a plurality of paths, and an amplitude-phase control section which controls a reference signal selection operation of the switch bank on the basis of an input signal.

Abstract translation: 本发明提供一种DAC（数模转换器），能够产生具有用于降低期望频带中的误差信号电平的陷波的传递函数。 本发明的DAC包括一个开关组，输入至少两个参考信号并选择这些信号中的任一个并通过多条路径输出所选择的信号;以及幅度相位控制部分，其控制参考信号选择 根据输入信号对开关组进行操作。

公开(公告)号：US08264387B2

公开(公告)日：2012-09-11

申请号：US11396097

申请日：2006-03-31

Applicant: Lawrence Der ,  George Tyson Tuttle ,  Alessandro Piovaccari ,  Chunyu Xin ,  Scott Haban ,  Javier Elenes ,  Dan Kasha ,  Peter Vancorenland

Inventor： Lawrence Der ,  George Tyson Tuttle ,  Alessandro Piovaccari ,  Chunyu Xin ,  Scott Haban ,  Javier Elenes ,  Dan Kasha ,  Peter Vancorenland

IPC: H03M1/00

CPC classification number: H04B1/40 ,  H03M3/398 ,  H03M3/40 ,  H03M3/448 ,  H03M3/452 ,  H03M3/50

Abstract: A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.

Abstract translation: 收发器包括一个处理器和一个模拟 - 数字转换器。 处理器适于在收发器的发射模式中，响应于第一数字信号产生调制信号。 在收发器的接收模式中，处理器适于响应于第二数字信号产生解调信号。 模数转换器以发送模式提供第一数字信号，并在接收模式下提供第二数字信号。

公开(公告)号：US07956781B2

公开(公告)日：2011-06-07

申请号：US12445029

申请日：2006-10-13

Applicant: Omid Oliaei ,  Alan Bannon ,  Anthony Dunne ,  Matthew R. Miller ,  Daniel O'Hare

Inventor： Omid Oliaei ,  Alan Bannon ,  Anthony Dunne ,  Matthew R. Miller ,  Daniel O'Hare

IPC: H03M3/00

CPC classification number: H03M3/392 ,  H03M3/40

Abstract: An analogue-to-digital converter apparatus comprises a first integrator coupled to a second integrator. The first and second integrators are coupled so as to provide a complex pole. The first integrator is selectively electrically decoupleable from the second integrator, thereby removing the complex pole.

Abstract translation: 模数转换器装置包括耦合到第二积分器的第一积分器。 第一和第二积分器耦合以提供复极。 第一积分器选择性地与第二积分器电可去耦，从而去除复极。

公开(公告)号：US20110069784A1

公开(公告)日：2011-03-24

申请号：US12948200

申请日：2010-11-17

Applicant: Eugene M. Petilli

Inventor： Eugene M. Petilli

IPC: H04L27/12 ,  H04L25/03

CPC classification number: H04B1/28 ,  H03M3/364 ,  H03M3/40 ,  H03M3/41 ,  H03M3/438 ,  H03M3/496 ,  H04B1/001 ,  H04B1/0017 ,  H04B1/0025

Abstract: Disclosed are hybrid heterodyne transmitters and receivers for use in communications systems, or other systems, and the corresponding methods for hybrid heterodyne transmitting and receiving. A heterodyne receiver for converting a continuous time modulated signal to a discrete time digital baseband signal includes a sigma-delta modulator. The sigma-delta modulator is a signal-delta analog-to-digital converter constructed and arranged to receive a modulated signal at an RF carrier frequency and provide a quantized output at a first intermediate frequency. The heterodyne receiver may also include a digital mixer constructed and arranged to receive a data stream quantized by the sigma-delta analog-to-digital converter and receive a signal at a second mixing frequency. The digital mixer then provides digital signals representative of a baseband signal suitable for digital signal processing.

Abstract translation: 公开了用于通信系统或其他系统的混合外差发射机和接收机以及用于混合外差发射和接收的相应方法。 用于将连续时间调制信号转换为离散时间数字基带信号的外差接收器包括Σ-Δ调制器。 Σ-Δ调制器是构造和布置成以RF载波频率接收调制信号的信号-δ模数转换器，并以第一中频提供量化输出。 外差接收机还可以包括构造和布置成接收由Σ-Δ模数转换器量化并以第二混频器接收信号的数据流的数字混频器。 然后，数字混合器提供表示适合于数字信号处理的基带信号的数字信号。