公开(公告)号：US08737108B2

公开(公告)日：2014-05-27

申请号：US13626720

申请日：2012-09-25

Applicant: Ruchir Saraswat ,  Matthias Gries

Inventor： Ruchir Saraswat ,  Matthias Gries

IPC: G11C5/02 ,  G11C5/04

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.

Abstract translation: 可配置性能和功耗的3D内存。 存储器件的实施例包括包括多个存储器管芯的动态随机存取存储器（DRAM），每个存储器管芯包括多个存储器阵列，每个存储器阵列包括外围逻辑电路和可配置逻辑。 存储器件还包括与DRAM耦合的系统元件，系统元件包括存储器控制器。 存储器控制器旨在提供对可配置逻辑的控制以提供用于一个或多个存储器阵列的单独或共享的外围逻辑电路，所述可配置逻辑可配置为启用或禁用外围逻辑电路中的一个或多个并启用或禁用 存储器阵列之间的一个或多个I / O连接。

公开(公告)号：US20140085959A1

公开(公告)日：2014-03-27

申请号：US13626720

申请日：2012-09-25

Applicant: Ruchir Saraswat ,  Matthias Gries

Inventor： Ruchir Saraswat ,  Matthias Gries

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.

Abstract translation: 可配置性能和功耗的3D内存。 存储器件的实施例包括包括多个存储器管芯的动态随机存取存储器（DRAM），每个存储器管芯包括多个存储器阵列，每个存储器阵列包括外围逻辑电路和可配置逻辑。 存储器件还包括与DRAM耦合的系统元件，系统元件包括存储器控制器。 存储器控制器旨在提供对可配置逻辑的控制以提供用于一个或多个存储器阵列的单独或共享的外围逻辑电路，所述可配置逻辑可配置为启用或禁用外围逻辑电路中的一个或多个并启用或禁用 存储器阵列之间的一个或多个I / O连接。

公开(公告)号：US20130246734A1

公开(公告)日：2013-09-19

申请号：US13419172

申请日：2012-03-13

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/00

CPC classification number: G06F12/063 ,  G06F11/3409 ,  G06F12/0292 ,  G06F12/0646 ,  G06F12/10 ,  Y02D10/13 ,  Y02D10/34

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。