公开(公告)号：US20130246734A1

公开(公告)日：2013-09-19

申请号：US13419172

申请日：2012-03-13

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/00

CPC classification number: G06F12/063 ,  G06F11/3409 ,  G06F12/0292 ,  G06F12/0646 ,  G06F12/10 ,  Y02D10/13 ,  Y02D10/34

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US09026767B2

公开(公告)日：2015-05-05

申请号：US13419172

申请日：2012-03-13

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/10 ,  G06F12/06

CPC classification number: G06F12/063 ,  G06F11/3409 ,  G06F12/0292 ,  G06F12/0646 ,  G06F12/10 ,  Y02D10/13 ,  Y02D10/34

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US08135936B2

公开(公告)日：2012-03-13

申请号：US12646248

申请日：2009-12-23

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/06 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0607 ,  Y02D10/13

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US20110153908A1

公开(公告)日：2011-06-23

申请号：US12646248

申请日：2009-12-23

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/06 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0607 ,  Y02D10/13

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。

公开(公告)号：US20140085959A1

公开(公告)日：2014-03-27

申请号：US13626720

申请日：2012-09-25

Applicant: Ruchir Saraswat ,  Matthias Gries

Inventor： Ruchir Saraswat ,  Matthias Gries

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.

Abstract translation: 可配置性能和功耗的3D内存。 存储器件的实施例包括包括多个存储器管芯的动态随机存取存储器（DRAM），每个存储器管芯包括多个存储器阵列，每个存储器阵列包括外围逻辑电路和可配置逻辑。 存储器件还包括与DRAM耦合的系统元件，系统元件包括存储器控制器。 存储器控制器旨在提供对可配置逻辑的控制以提供用于一个或多个存储器阵列的单独或共享的外围逻辑电路，所述可配置逻辑可配置为启用或禁用外围逻辑电路中的一个或多个并启用或禁用 存储器阵列之间的一个或多个I / O连接。

公开(公告)号：US20140181367A1

公开(公告)日：2014-06-26

申请号：US13726303

申请日：2012-12-24

Applicant: Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

Inventor： Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

IPC: G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0643 ,  G06F3/0679 ,  G06F9/5061 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  Y02D10/13

Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与非易失性存储器上的数据结构的瞬态和持久状态之间就地改变相关的方法和装置。 在一个实施例中，控制器逻辑引起一个或多个非易失性存储器件的第一部分在持久状态和瞬态之间的状态的改变，而不移动存储在一个或多个非易失性存储器件的第一部分中的数据 存储设备。 还公开并要求保护其他实施例。

公开(公告)号：US20070113113A1

公开(公告)日：2007-05-17

申请号：US11539121

申请日：2006-10-05

Applicant: Christian Sauer ,  Soeren Sonntag ,  Matthias Gries

Inventor： Christian Sauer ,  Soeren Sonntag ,  Matthias Gries

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/324 ,  Y02D10/126

Abstract: A data processing arrangement including a plurality of processing units. Each processing unit has a processing element, a data memory, a fill level unit, and a control unit. The processing element processes data stored in the data memory, or the data memory stores results of data processing performed by the processing element. The fill level unit generates a fill level signal signaling an amount of data stored in the data memory. The control unit controls processing power of the processing element based on the fill level signal.

Abstract translation: 一种数据处理装置，包括多个处理单元。 每个处理单元具有处理元件，数据存储器，填充级单元和控制单元。 处理元件处理存储在数据存储器中的数据，或者数据存储器存储由处理元件执行的数据处理的结果。 填充级别单元产生用于指示存储在数据存储器中的数据量的填充电平信号。 控制单元基于填充电平信号来控制处理元件的处理能力。

公开(公告)号：US09513692B2

公开(公告)日：2016-12-06

申请号：US14030515

申请日：2013-09-18

Applicant: Ruchir Saraswat ,  Matthias Gries ,  Nicholas P. Cowley

Inventor： Ruchir Saraswat ,  Matthias Gries ,  Nicholas P. Cowley

IPC: G06F1/32 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0685 ,  G06F12/02 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7211 ,  G11C5/025 ,  G11C5/14 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.

Abstract translation: 存储器控制器可操作用于对显示不同属性的存储器区域的选择性存储器访问，利用改变存取速度，保留时间和功耗的不同存储器能力等。 存储器的不同区域具有不同的属性，而作为可寻址存储器的单个连续范围，可用于应用。 存储器控制器采用识别计算设备的操作优先级的操作模式，例如速度，功率节省或效率。 存储器控制器基于存储在该区域中的数据的预期使用情况来识别存储器区域，例如指示将来检索的访问频率。 因此，存储器控制器基于操作模式和存储在该区域中的数据的预期使用量，根据启发式方式来选择存储器区域，该启发式方法基于那些呈现与数据的预期使用高度对应的属性的那些， 。

公开(公告)号：US09195577B2

公开(公告)日：2015-11-24

申请号：US13995899

申请日：2011-09-30

Applicant: Ruchir Saraswat ,  Matthias Gries

Inventor： Ruchir Saraswat ,  Matthias Gries

IPC: G06F12/00 ,  G11C7/04 ,  G11C11/406 ,  G11C5/02 ,  G06F1/20

CPC classification number: G06F12/00 ,  G06F1/206 ,  G11C5/025 ,  G11C7/04 ,  G11C11/40622 ,  G11C11/40626

Abstract: Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors.

Abstract translation: 使用热量数据的3D堆叠存储器的操作的动态操作。 存储器件的实施例包括具有多个耦合的存储器元件和多个热传感器的存储器，所述多个热传感器包括存储器堆叠的第一区域中的第一热传感器和存储器堆叠的第二区域中的第二热传感器。 存储器控制器至少部分地基于由热传感器产生的热信息来提供操作来修改存储元件的热条件。

公开(公告)号：US08737108B2

公开(公告)日：2014-05-27

申请号：US13626720

申请日：2012-09-25

Applicant: Ruchir Saraswat ,  Matthias Gries

Inventor： Ruchir Saraswat ,  Matthias Gries

IPC: G11C5/02 ,  G11C5/04

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.

Abstract translation: 可配置性能和功耗的3D内存。 存储器件的实施例包括包括多个存储器管芯的动态随机存取存储器（DRAM），每个存储器管芯包括多个存储器阵列，每个存储器阵列包括外围逻辑电路和可配置逻辑。 存储器件还包括与DRAM耦合的系统元件，系统元件包括存储器控制器。 存储器控制器旨在提供对可配置逻辑的控制以提供用于一个或多个存储器阵列的单独或共享的外围逻辑电路，所述可配置逻辑可配置为启用或禁用外围逻辑电路中的一个或多个并启用或禁用 存储器阵列之间的一个或多个I / O连接。