公开(公告)号：US5809228A

公开(公告)日：1998-09-15

申请号：US579414

申请日：1995-12-27

Applicant: Brian K. Langendorf ,  Michael Derr

Inventor： Brian K. Langendorf ,  Michael Derr

IPC: G01R31/28 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F11/00

CPC classification number: G06F11/1056 ,  G06F12/0215

Abstract: Apparatus and a method for testing each write to memory to determine whether it is addressed to an address identical to that of another write to memory waiting to be processed and merging the valid data in any subsequent writes to the same address until a memory write occurs.

Abstract translation: 用于测试对存储器的每次写入的装置和方法，以确定其是否寻址到等待被处理的另一写入存储器的地址的地址，并且将任何后续写入中的有效数据合并到同一地址，直到存储器写入发生。

公开(公告)号：US20070234433A1

公开(公告)日：2007-10-04

申请号：US11395468

申请日：2006-03-30

Applicant: Kah Yeem ,  Thian Tan ,  Kar Wong ,  Michael Derr

Inventor： Kah Yeem ,  Thian Tan ,  Kar Wong ,  Michael Derr

IPC: H04N7/16

CPC classification number: G06F21/572

Abstract: An embodiment of the present invention is a technique to provide a secure authentication of chipset configuration. A first chipset configuration (CC) register set in an input/output (I/O) manageability engine (ME) partition authenticates and controls enabling a CC functionality. The I/O ME partition manages I/O resources shared with a processor in a secure manner. A second CC register set in a processor interface space provides the CC functionality. The second CC register set includes a global enable register having an enable field securely accessible to the I/O ME partition in a read and write-once accessibility and accessible to the processor via the processor interface space in a read-only accessibility.

Abstract translation: 本发明的实施例是提供芯片组配置的安全认证的技术。 在输入/输出（I / O）可管理性引擎（ME）分区中设置的第一个芯片组配置（CC）寄存器对CC功能进行认证和控制。 I / O ME分区以安全的方式管理与处理器共享的I / O资源。 在处理器接口空间中设置的第二个CC寄存器提供CC功能。 第二CC寄存器集包括全局使能寄存器，其具有可读取和写入一次可访问性并且可通过处理器接口空间在只读可访问性中对处理器可访问的I / O ME分区可安全访问的使能字段。

公开(公告)号：US20060123180A1

公开(公告)日：2006-06-08

申请号：US11004011

申请日：2004-12-02

Applicant: Michael Derr ,  John Howard ,  Darren Abramson ,  Leslie Cline ,  Rob Strong

Inventor： Michael Derr ,  John Howard ,  Darren Abramson ,  Leslie Cline ,  Rob Strong

IPC: G06F13/36

CPC classification number: G06F13/28 ,  G06F2213/0042 ,  Y02D10/14

Abstract: A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.

Abstract translation: 描述了用于监控未来通用串行总线（USB）活动的电路。 具体地，电路可以包括直接存储器访问（DMA）引擎调度预取器。 DMA引擎调度预取器访问主内存中的链表列表调度结构。 对结构进行检查，以便链接列表安排USB活动的未来帧。 周期性DMA引擎随后仅在安排USB流量的帧期间访问主存储器。

公开(公告)号：US20060004928A1

公开(公告)日：2006-01-05

申请号：US10883518

申请日：2004-06-30

Applicant: Gary Hess ,  Robert Strong ,  Jeffrey Brown ,  Michael Derr

Inventor： Gary Hess ,  Robert Strong ,  Jeffrey Brown ,  Michael Derr

IPC: G06F13/00

CPC classification number: G06F21/71 ,  G06F21/10 ,  G06F21/78 ,  G06F21/82 ,  G06F2221/2101

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises determining whether a feature on a device is permitted to be enabled, determining whether a total number of enabled features on the device is less than or equal to a maximum number of allowable features on the device, and allowing the enabling of the device feature if the device feature is permitted to be enabled and the total number of enabled features on the device is less than or equal to the maximum number of allowable features on the device.