公开(公告)号：US20060123180A1

公开(公告)日：2006-06-08

申请号：US11004011

申请日：2004-12-02

申请人： Michael Derr ,  John Howard ,  Darren Abramson ,  Leslie Cline ,  Rob Strong

发明人： Michael Derr ,  John Howard ,  Darren Abramson ,  Leslie Cline ,  Rob Strong

IPC分类号： G06F13/36

CPC分类号： G06F13/28 ,  G06F2213/0042 ,  Y02D10/14

摘要： A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.

摘要翻译： 描述了用于监控未来通用串行总线（USB）活动的电路。 具体地，电路可以包括直接存储器访问（DMA）引擎调度预取器。 DMA引擎调度预取器访问主内存中的链表列表调度结构。 对结构进行检查，以便链接列表安排USB活动的未来帧。 周期性DMA引擎随后仅在安排USB流量的帧期间访问主存储器。

公开(公告)号：US20070233909A1

公开(公告)日：2007-10-04

申请号：US11395678

申请日：2006-03-30

申请人： Michael Derr ,  Darren Abramson ,  Bryan Doucette ,  Karthi Vadivelu

发明人： Michael Derr ,  Darren Abramson ,  Bryan Doucette ,  Karthi Vadivelu

IPC分类号： G06F3/00 ,  G06F13/14

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

摘要翻译： 一种以非均匀帧速率同步多个主机控制器的方法，装置和系统。 该装置包括第一主机控制器，第二主机控制器和逻辑。 第一主机控制器被配置为以第一帧速率访问存储器。 第二主机控制器被配置为以与第一帧速率不同的第二帧速率访问存储器。 该逻辑耦合到第一和第二主机控制器以以公共帧速率同步第一和第二主机控制器的存储器访问。 描述其他实施例。

公开(公告)号：US5889968A

公开(公告)日：1999-03-30

申请号：US939801

申请日：1997-09-30

申请人： Joseph A. Bennett ,  Darren Abramson ,  Michael Derr ,  Zohar Bogin

发明人： Joseph A. Bennett ,  Darren Abramson ,  Michael Derr ,  Zohar Bogin

IPC分类号： G06F13/36 ,  G06F13/14

CPC分类号： G06F13/36

摘要： A method and apparatus is disclosed for providing an interlocked broadcast message that solves the problem of a system component taking action in response to a broadcast message issued by a processor before the processor receives communication that the broadcast message has been delivered. A broadcast message transaction request is issued from a processor. The broadcast message transaction request is posted in a transaction request buffer. A reply is communicated to the processor that the broadcast message transaction request has been posted, and the broadcast message is then delivered over the bus. In an alternative embodiment, after the broadcast message transaction request is issued from the processor, the broadcast message transaction request is stored in a transaction request buffer. The broadcast message is only delivered over the bus once it has been determined that the reply to the processor that the broadcast message transaction has completed can be immediately delivered to the processor following the delivery of the broadcast message.

摘要翻译： 公开了一种用于提供互锁广播消息的方法和装置，其解决了在处理器接收到广播消息已被传送的通信之前响应于由处理器发出的广播消息而采取动作的系统组件的问题。 从处理器发出广播消息交易请求。 广播消息事务请求被发布在事务请求缓冲器中。 向处理器传送广播消息交易请求已经被发布的答复，然后通过总线传送广播消息。 在替代实施例中，在从处理器发出广播消息事务请求之后，广播消息事务请求被存储在事务请求缓冲器中。 一旦确定广播消息交易已经完成的对处理器的答复可以在传送广播消息之后立即传送到处理器，广播消息仅在总线上传送。

公开(公告)号：US20060200690A1

公开(公告)日：2006-09-07

申请号：US11074233

申请日：2005-03-05

申请人： Leslie Cline ,  Siripong Sritanyaratana ,  Alon Naveh ,  Shai Rotem ,  Eric Samson ,  Michael Derr

发明人： Leslie Cline ,  Siripong Sritanyaratana ,  Alon Naveh ,  Shai Rotem ,  Eric Samson ,  Michael Derr

IPC分类号： G06F1/32

CPC分类号： G06F12/0835 ,  G06F2212/1028 ,  Y02D10/13

摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

公开(公告)号：US07900072B2

公开(公告)日：2011-03-01

申请号：US11963215

申请日：2007-12-21

申请人： Michael Berger ,  Michael Derr ,  Joshua Resch ,  Mukesh Kataria ,  Mazen Gedeon ,  Eli Kupermann ,  Jeffrey John Vick

发明人： Michael Berger ,  Michael Derr ,  Joshua Resch ,  Mukesh Kataria ,  Mazen Gedeon ,  Eli Kupermann ,  Jeffrey John Vick

IPC分类号： G06F1/00 ,  G06F1/26 ,  H04M1/00 ,  G11C5/14

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

摘要： Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.

摘要翻译： 各种实施例针对包含微控制器的架构的三层电力方案。 在一个实施例中，电源管理系统可以包括芯片组中的微控制器，以及用于控制对微控制器的电源的低功耗电力，以及功率控制器以便很好地控制对低功耗电力的供电。 电源管理系统可以被布置成在多个功耗状态之间切换。 在最大功耗状态下，微控制器打开，电源控制器打开，低功耗电源正常。 在中间功耗状态下，微控制器关闭，电源控制器处于打开状态，低功耗电源需要打开。 在最小功耗状态下，微控制器处于关闭状态，功率控制器处于开启状态，低功耗状态可以根据电源控制器选择开启或关闭。 描述和要求保护其他实施例。

公开(公告)号：US20050223292A1

公开(公告)日：2005-10-06

申请号：US10781371

申请日：2004-02-17

申请人： Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

发明人： Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

IPC分类号： G06F11/00

CPC分类号： G06F8/60

摘要： A patch mechanism is described, which can be used to detect and workaround defects and conditions existing in an integrated circuit chip. The patch mechanism includes a trigger-matching logic incorporated within an integrated circuit chip to capture an incoming request cycle and determine if the captured incoming cycle matches one or more of trigger conditions. The patch mechanism further includes a control logic coupled to the trigger-matching logic to select a set of instructions upon detection of at least one matched trigger condition and to execute operations corresponding to the selected set of instructions. The control logic is configured to select the set of instructions based on the at least one matched trigger condition.

摘要翻译： 描述了一种补丁机制，可用于检测和解决集成电路芯片中存在的缺陷和状况。 补丁机制包括一个集成在集成电路芯片内的触发器匹配逻辑，以捕获进入的请求周期并确定捕获的进入周期是否匹配一个或多个触发条件。 补丁机制还包括耦合到触发匹配逻辑的控制逻辑，以在检测到至少一个匹配的触发条件时选择一组指令，并执行与所选指令集相对应的操作。 所述控制逻辑被配置为基于所述至少一个匹配的触发条件来选择所述指令集。

公开(公告)号：US08463968B2

公开(公告)日：2013-06-11

申请号：US11096941

申请日：2005-03-31

申请人： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

发明人： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F13/362

CPC分类号： G06F13/4291

摘要： According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.

摘要翻译： 根据一个实施例，公开了一种计算机系统。 计算机系统包括闪速存储器件，耦合到闪存器件的串行外设接口（SPI），耦合到SPI的网络控制器; 以及耦合到SPI的芯片组。 芯片组包括仲裁器，用于在网络控制器和芯片组之间进行仲裁，以控制SPI以访问闪存设备。

公开(公告)号：US5809228A

公开(公告)日：1998-09-15

申请号：US579414

申请日：1995-12-27

申请人： Brian K. Langendorf ,  Michael Derr

发明人： Brian K. Langendorf ,  Michael Derr

IPC分类号： G01R31/28 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F11/00

CPC分类号： G06F11/1056 ,  G06F12/0215

摘要： Apparatus and a method for testing each write to memory to determine whether it is addressed to an address identical to that of another write to memory waiting to be processed and merging the valid data in any subsequent writes to the same address until a memory write occurs.

摘要翻译： 用于测试对存储器的每次写入的装置和方法，以确定其是否寻址到等待被处理的另一写入存储器的地址的地址，并且将任何后续写入中的有效数据合并到同一地址，直到存储器写入发生。

公开(公告)号：US20070234433A1

公开(公告)日：2007-10-04

申请号：US11395468

申请日：2006-03-30

申请人： Kah Yeem ,  Thian Tan ,  Kar Wong ,  Michael Derr

发明人： Kah Yeem ,  Thian Tan ,  Kar Wong ,  Michael Derr

IPC分类号： H04N7/16

CPC分类号： G06F21/572

摘要： An embodiment of the present invention is a technique to provide a secure authentication of chipset configuration. A first chipset configuration (CC) register set in an input/output (I/O) manageability engine (ME) partition authenticates and controls enabling a CC functionality. The I/O ME partition manages I/O resources shared with a processor in a secure manner. A second CC register set in a processor interface space provides the CC functionality. The second CC register set includes a global enable register having an enable field securely accessible to the I/O ME partition in a read and write-once accessibility and accessible to the processor via the processor interface space in a read-only accessibility.

摘要翻译： 本发明的实施例是提供芯片组配置的安全认证的技术。 在输入/输出（I / O）可管理性引擎（ME）分区中设置的第一个芯片组配置（CC）寄存器对CC功能进行认证和控制。 I / O ME分区以安全的方式管理与处理器共享的I / O资源。 在处理器接口空间中设置的第二个CC寄存器提供CC功能。 第二CC寄存器集包括全局使能寄存器，其具有可读取和写入一次可访问性并且可通过处理器接口空间在只读可访问性中对处理器可访问的I / O ME分区可安全访问的使能字段。

公开(公告)号：US20060004928A1

公开(公告)日：2006-01-05

申请号：US10883518

申请日：2004-06-30

申请人： Gary Hess ,  Robert Strong ,  Jeffrey Brown ,  Michael Derr

发明人： Gary Hess ,  Robert Strong ,  Jeffrey Brown ,  Michael Derr

IPC分类号： G06F13/00

CPC分类号： G06F21/71 ,  G06F21/10 ,  G06F21/78 ,  G06F21/82 ,  G06F2221/2101

摘要： A method, apparatus, and system are disclosed. In one embodiment the method comprises determining whether a feature on a device is permitted to be enabled, determining whether a total number of enabled features on the device is less than or equal to a maximum number of allowable features on the device, and allowing the enabling of the device feature if the device feature is permitted to be enabled and the total number of enabled features on the device is less than or equal to the maximum number of allowable features on the device.