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    Phase change memory device generating program current and method thereof
    11.
    发明授权
    Phase change memory device generating program current and method thereof 有权
    相变存储器件产生程序电流及其方法

    公开(公告)号：US08259511B2

    公开(公告)日：2012-09-04

    申请号：US13064672

    申请日：2011-04-07

    Applicant: Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    Inventor： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC: G11C7/10

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

    Abstract translation: 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

    PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING READ OPERATION THEREOF
    12.
    发明申请
    PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING READ OPERATION THEREOF 审中-公开
    相变随机访问存储器及其读取操作的方法

    公开(公告)号：US20100220522A1

    公开(公告)日：2010-09-02

    申请号：US12777298

    申请日：2010-05-11

    Applicant: Hyung-rok Oh ,  Mu-hui Park ,  Du-eung Kim

    Inventor： Hyung-rok Oh ,  Mu-hui Park ,  Du-eung Kim

    IPC: G11C11/00 ,  G11C8/08

    CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/004

    Abstract: A phase change random access memory is provided which includes a memory array including a plurality of phase change memory cells, and wordlines respectively connected to the phase change memory cells, where, in a read operation, a voltage of a wordline connected to a selected phase change memory cell is transitioned between at least two voltage stages having different voltage levels.

    Abstract translation: 提供了一种相变随机存取存储器，其包括包括多个相变存储器单元的存储器阵列和分别连接到相变存储单元的字线，其中在读操作中连接到所选相位的字线的电压 改变存储单元在具有不同电压电平的至少两个电压级之间转变。

    PHASE CHANGE RANDOM ACCESS MEMORY DEVICE
    13.
    发明申请
    PHASE CHANGE RANDOM ACCESS MEMORY DEVICE 有权
    相变随机访问存储器件

    公开(公告)号：US20080062751A1

    公开(公告)日：2008-03-13

    申请号：US11850125

    申请日：2007-09-05

    Applicant: Mu-hui PARK ,  Beak-hyung CHO ,  Hyung-rok OH

    Inventor： Mu-hui PARK ,  Beak-hyung CHO ,  Hyung-rok OH

    IPC: G11C11/00

    CPC classification number: G11C13/0064 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

    Abstract: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

    Abstract translation: 在相变随机存取存储器（PRAM）装置中，通过将设置的脉冲施加到失败的PRAM单元来执行写入操作。 设置脉冲包括从第一电流幅度顺序地减小到第二电流幅度的多个级。 第一电流幅度或第二电流幅度从一个写入环路变化到另一个写入环路。

    PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE
    14.
    发明申请
    PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE 审中-公开
    相变随机访问存储器件

    公开(公告)号：US20100124101A1

    公开(公告)日：2010-05-20

    申请号：US12499894

    申请日：2009-07-09

    Applicant: Mu-hui Park ,  Soo-guil Yang ,  Kwang-ho Kim

    Inventor： Mu-hui Park ,  Soo-guil Yang ,  Kwang-ho Kim

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/004 ,  G11C7/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C2013/0054

    Abstract: Provided is a phase-change random access memory device. The phase-change random access memory device includes a phase-change memory cell array having multiple phase-change memory cells, a sensing unit and a discharge unit. The sensing unit detects data, stored in a phase-change memory cell to be sensed of the multiple phase-change memory cells, during a sensing period. The discharge unit discharges at least one node of multiple nodes positioned on a sensing path between the phase-change memory cell array and the sensing unit during a period other than the sensing period.

    Abstract translation: 提供了相变随机存取存储器件。 相变随机存取存储装置包括具有多个相变存储单元的相变存储单元阵列，感测单元和放电单元。 感测单元在感测周期期间检测存储在要被感测的多个相变存储器单元的相变存储单元中的数据。 放电单元在除了感测周期之外的时段期间放电位于相变存储单元阵列和感测单元之间的感测路径上的多个节点的至少一个节点。

    PHASE CHANGE RANDOM ACCESS MEMORY DEVICE
    15.
    发明申请
    PHASE CHANGE RANDOM ACCESS MEMORY DEVICE 有权
    相变随机访问存储器件

    公开(公告)号：US20100118601A1

    公开(公告)日：2010-05-13

    申请号：US12690999

    申请日：2010-01-21

    Applicant: Mu-hui PARK ,  Beak-hyung CHO ,  Hyung-rok OH

    Inventor： Mu-hui PARK ,  Beak-hyung CHO ,  Hyung-rok OH

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0064 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

    Abstract: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

    Abstract translation: 在相变随机存取存储器（PRAM）装置中，通过将设置的脉冲施加到失败的PRAM单元来执行写入操作。 设置脉冲包括从第一电流幅度顺序地减小到第二电流幅度的多个级。 第一电流幅度或第二电流幅度从一个写入环路变化到另一个写入环路。

    Phase change random access memory device
    16.
    发明授权
    Phase change random access memory device 有权
    相变随机存取存储器件

    公开(公告)号：US07672156B2

    公开(公告)日：2010-03-02

    申请号：US11850125

    申请日：2007-09-05

    Applicant: Mu-hui Park ,  Beak-hyung Cho ,  Hyung-rok Oh

    Inventor： Mu-hui Park ,  Beak-hyung Cho ,  Hyung-rok Oh

    IPC: G11C11/00

    CPC classification number: G11C13/0064 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

    Abstract: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

    Abstract translation: 在相变随机存取存储器（PRAM）装置中，通过将设置的脉冲施加到失败的PRAM单元来执行写入操作。 设置脉冲包括从第一电流幅度顺序地减小到第二电流幅度的多个级。 第一电流幅度或第二电流幅度从一个写入环路变化到另一个写入环路。

    Phase change memory device generating program current and method thereof
    18.
    发明申请
    Phase change memory device generating program current and method thereof 有权
    相变存储器件产生程序电流及其方法

    公开(公告)号：US20080062753A1

    公开(公告)日：2008-03-13

    申请号：US11898045

    申请日：2007-09-07

    Applicant: Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    Inventor： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

    Abstract translation: 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

    Phase change memory device generating program current and method thereof
    19.
    发明申请
    Phase change memory device generating program current and method thereof 有权
    相变存储器件产生程序电流及其方法

    公开(公告)号：US20100110781A1

    公开(公告)日：2010-05-06

    申请号：US12654338

    申请日：2009-12-17

    Applicant: Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    Inventor： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC: G11C11/00 ,  G11C7/10 ,  G11C17/16

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

    Abstract translation: 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

    Bias voltage generator and method generating bias voltage for semiconductor memory device
    20.
    发明授权
    Bias voltage generator and method generating bias voltage for semiconductor memory device 有权
    用于半导体存储器件的偏置电压发生器和产生偏置电压的方法

    公开(公告)号：US07548467B2

    公开(公告)日：2009-06-16

    申请号：US11955562

    申请日：2007-12-13

    Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC: G11C5/14

    CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

    Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。

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