公开(公告)号：US07286176B2

公开(公告)日：2007-10-23

申请号：US10820577

申请日：2004-04-08

申请人： Douglas R. Holberg ,  Sandra M. Johnson ,  Nadi R. Itani ,  Argos R. Cue

发明人： Douglas R. Holberg ,  Sandra M. Johnson ,  Nadi R. Itani ,  Argos R. Cue

IPC分类号： H04N5/222 ,  H04N5/228 ,  H03M1/12 ,  H03M1/38

CPC分类号： H04N5/23241 ,  H04N5/23293 ,  H04N5/335

摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直 由处理系统本身本地生成的系统的定时信号。 处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平 定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。 处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。 该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。 单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显​​示启用所选数据分辨率级别的电路。

公开(公告)号：US06720999B1

公开(公告)日：2004-04-13

申请号：US09283112

申请日：1999-03-31

申请人： Douglas R. Holberg ,  Sandra M. Johnson ,  Nadi R. Itani ,  Argos R. Cue

发明人： Douglas R. Holberg ,  Sandra M. Johnson ,  Nadi R. Itani ,  Argos R. Cue

IPC分类号： H04N5228

CPC分类号： H04N5/23241 ,  H04N5/23293 ,  H04N5/335

摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit formats corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括多模，多电流电平，相关双样本和可变增益（CDS / VGA）电路，用于从CCD系统接收数据，受水平和垂直 由处理系统本身本地生成的系统的定时信号。 处理系统特别地包括可编程定时电路，用于通过驱动高频水平定时电路的可编程低频主垂直定时电路来控制来自二维像素阵列的元件的像素强度值的检测，其中垂直和水平 定时信号从模拟处理器独立地本地提供给阵列，实际上对阵列进行采样。 处理系统的架构还包括相关双采样器，黑电平钳位器和A / D转换模块。 该处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以实现减少的数据分辨率; 具有可选位宽输出并耦合到所述VGA电路的数模转换器（ADC），以及耦合到所述ADC的增益电路。 单芯片模拟前端以对应于所选电流和数据分辨率的位格式生成数字化CCD数据。 VGA放大器包括分别为静止图像拍摄和在另一个观看屏幕上分离的视频显​​示启用所选数据分辨率级别的电路。

公开(公告)号：US06707492B1

公开(公告)日：2004-03-16

申请号：US09282523

申请日：1999-03-31

申请人： Nadi R. Itani

发明人： Nadi R. Itani

IPC分类号： H04N5235

CPC分类号： H03M1/187 ,  H04N5/243

摘要： A gain characteristic correctable dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system correctably extends the dynamic range of the imager device, subject to offsets providing linearity corrections at predetermined trip points, subject to determined offset values, to ensure that there are no discontinuities in the system transfer function.

摘要翻译： 增益特性可校正动态范围增强系统（DRES）从连接到相关双采样（CDS）电路的成像器装置接收输入信号，用于从CCD成像装置接收视频信号。 动态范围增强系统包括可变增益放大器（VGA）和有限位宽模数转换器（ADC），数字化从VGA接收的模拟信号。 ADC的输出被提供给连接到ADC的输出的较宽位移移位器的初始位范围位置。 DRES系统可校正地扩展成像器装置的动态范围，经受偏移量，在预定的跳变点提供线性校正，以确定偏移值，以确保系统传递功能中不存在不连续性。

公开(公告)号：US06252536B1

公开(公告)日：2001-06-26

申请号：US09283779

申请日：1999-03-31

申请人： Sandra M. Johnson ,  Nadi R. Itani

发明人： Sandra M. Johnson ,  Nadi R. Itani

IPC分类号： H03M112

CPC分类号： H04N5/361 ,  H03M1/18 ,  H03M1/187

摘要： A dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system includes a 2-bit ADC for extending the dynamic range of the imager device, which enhances the dynamic range of a 10 bit ADC to 13 bits.

摘要翻译： 动态范围增强系统（DRES）从连接到相关双采样（CDS）电路的成像器装置接收输入信号，用于从CCD成像装置接收视频信号。 动态范围增强系统包括可变增益放大器（VGA）和有限位宽模数转换器（ADC），数字化从VGA接收的模拟信号。 ADC的输出被提供给连接到ADC的输出的较宽位移移位器的初始位范围位置。 DRES系统包括一个2位ADC，用于扩展成像器件的动态范围，从而将10位ADC的动态范围增加到13位。