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公开(公告)号：US20240283460A1
公开(公告)日：2024-08-22
申请号：US18171211
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
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公开(公告)号：US11899878B2
公开(公告)日：2024-02-13
申请号：US18148253
申请日：2022-12-29
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Choon Hyop Lee , Jang Hui Kim , Jae Won Kim , In Nam Lee
CPC classification number: G06F3/04166 , G06F3/044 , G06F3/04164 , H03M1/18
Abstract: An input sensing device includes driving electrodes and sensing electrodes, and an analog front-end which processes sensing signals from the sensing electrodes to output a differential output value. The analog front-end includes a first charge amplifier which differentially amplifies first and second sensing signals from two sensing electrodes to first and second input terminals, thus outputting first and second differential signals through first and second output terminals, a second charge amplifier which differentially amplifies the first and second differential signals, thus outputting third and fourth differential signals, a first demodulation circuit which filters the first and second differential signals in a first mode and filters each of the third and fourth differential signals in a second mode, and a first analog-to-digital converter which outputs a first sensing value based on at least one output signal of the first demodulation circuit.
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公开(公告)号：US11876539B2
公开(公告)日：2024-01-16
申请号：US17637186
申请日：2020-08-20
Applicant: ams International AG
Inventor： Srinidhi Koushik Kanagal Ramesh , Thomas Fröhlich
CPC classification number: H03M3/412 , H03F3/45475 , H03M1/18 , H03M1/66 , H03F2200/18
Abstract: A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.
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公开(公告)号：US11737698B2
公开(公告)日：2023-08-29
申请号：US16979792
申请日：2019-03-12
Applicant: CathVision ApS
Inventor： Sigge Nejst Larsen , Victor Shadbolt , David P. MacAdam , Harold Wodlinger
Abstract: An electrophysiology system including signal channels each of which processes an electrophysiological signal along a signal path extending from an input port that receives the analog electrophysiological signal, via an adjustable gain element that amplifies the electrophysiological signal, and via an ADC element that converts the analog signal into a corresponding digital signal, to an output port. The system further includes a monitoring element that generates a monitoring signal representative of a DC component of the electrophysiological signal and a gain control element that generates a control signal responsive to the monitoring signal. The control signal controls the gain setting of the gain element to cause a decrease in gain, if an increase in the magnitude of the DC component is determined; and/or an increase in gain, if a decrease in the magnitude of the DC component is determined.
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公开(公告)号：US11659329B2
公开(公告)日：2023-05-23
申请号：US17395077
申请日：2021-08-05
Applicant: Infineon Technologies AG
Inventor： Dietmar Straeussnigg
Abstract: A digital microphone includes at least one integrator; a state detection and parameter control component directly coupled to an output of the integrator; and a signal processing component coupled to an output of the state detection and parameter control component, wherein a parameter of the signal processing component includes a first value in a first operational mode and a second value in a second operational mode different from the first operational mode.
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Patent Agency Ranking
公开(公告)号：US20190123753A1
公开(公告)日：2019-04-25
申请号：US16164015
申请日：2018-10-18
Applicant: Infineon Technologies AG
Inventor： Dietmar Straeussnigg
CPC classification number: H03M1/201 , H03M1/1245 , H03M1/18 , H03M3/33 , H03M3/468
Abstract: In accordance with an embodiment, a method includes adding a dither signal to a first signal to generate a second signal, subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal, performing a first sigma delta conversion of the second signal to a digital fourth signal, performing a second signal delta conversion of the third signal to a digital fifth signal, combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.
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公开(公告)号：US20180351523A1
公开(公告)日：2018-12-06
申请号：US15992847
申请日：2018-05-30
Inventor： John Paul LESSO
CPC classification number: H03G3/301 , H03F3/187 , H03F3/2175 , H03F2200/03 , H03G3/3005 , H03G3/3089 , H03G3/32 , H03M1/18 , H03M1/70 , H03M3/51 , H04R3/00 , H04R2430/01 , H04R2499/11
Abstract: This application relates to audio circuits, such as audio driving circuits, with improved audio performance. An audio arrangement (200) has an audio circuit (201) with a forward signal path between an input (102) for an input digital audio signal (DIN) and an output (103) for an output analogue audio signal (AOUT). The circuit also has a feedback path comprising an analogue-to-digital conversion module (202) for receiving an analogue feedback signal (VFB) derived from the output analogue audio signal and outputting a corresponding digital feedback signal (DFB). The analogue-to-digital conversion module (202) has an ADC (108), an analogue gain element (203) configured to apply analogue gain (GA) to the analogue feedback signal before the ADC and a digital gain element (204) for applying digital gain (GD) to a signal output from the ADC. A gain controller (205) controls the analogue gain and the digital gain applied based on the input digital audio signal (DIN).
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公开(公告)号：US20180269837A1
公开(公告)日：2018-09-20
申请号：US15918115
申请日：2018-03-12
Applicant: Holger Motzkau , Lars Andreas Rydh
Inventor： Holger Motzkau , Lars Andreas Rydh
CPC classification number: H03F1/02 , G01R19/0053 , G01R19/2509 , H03F3/04 , H03F2200/171 , H03F2200/372 , H03M1/00 , H03M1/18
Abstract: The disclosure relates to a lock-in amplifier comprising a plurality of channels (CH1-CHN), wherein each channel of the plurality of channels (CH1-CHN) is configured to receive an input signal (Sin1-SinN) and generate at least one output signal (Sout1-SoutN), a synchronization unit (110) configured to synchronize the generated output signals (Sout1-SoutN) of the plurality of channels (CH1-CHN), an aggregation module (150) configured to receive the generated output signals (Sout1-SoutN) and generate an aggregated signal (Sagg) based on the generated output signals (Sout1-SoutN).
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公开(公告)号：US20180198461A1
公开(公告)日：2018-07-12
申请号：US15915796
申请日：2018-03-08
Applicant: Microchip Technology Incorporated
Inventor： Bryan Kris , Neil Deutscher , Thomas S. Spohrer
CPC classification number: H03M1/34 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03M1/007 , H03M1/1009 , H03M1/1028 , H03M1/1057 , H03M1/1071 , H03M1/18 , H03M1/38 , H03M1/502
Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.
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公开(公告)号：US20180132750A1
公开(公告)日：2018-05-17
申请号：US15621621
申请日：2017-06-13
Applicant: Arthur J. Kalb , Yogesh Jayaraman Sharma , Marvin Liu Shu
Inventor： Arthur J. Kalb , Yogesh Jayaraman Sharma , Marvin Liu Shu
IPC: A61B5/0428 , A61B5/00 , A61B5/0452
CPC classification number: A61B5/04288 , A61B5/0006 , A61B5/0452 , A61B5/7207 , A61B5/7217 , A61B5/7225 , H03M1/0673 , H03M1/18 , H03M1/68 , H03M3/414 , H03M3/46
Abstract: An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.
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