公开(公告)号：US06750906B1

公开(公告)日：2004-06-15

申请号：US09075446

申请日：1998-05-08

申请人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

发明人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC分类号： H04N5235

CPC分类号： H04N5/2352

摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US6038116A

公开(公告)日：2000-03-14

申请号：US75449

申请日：1998-05-08

申请人： Douglas R. Holberg ,  Nadi R. Itani ,  David R. Welland

发明人： Douglas R. Holberg ,  Nadi R. Itani ,  David R. Welland

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0248

摘要： A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.

摘要翻译： 高压输入焊盘和接受静电放电（ESD）浪涌而不损坏输入半导体放大器的方法。 保护系统包括金属栅极晶体管和提供ESD保护的n阱电阻。 通过将输入双极结晶体管连接到放大器的负输入连接，进一步提供与放大器耦合的大电压的保护。 负极电流被引导到地，其阳极接地二极管在其阴极处连接到放大器的负输入连接。

公开(公告)号：US07719595B1

公开(公告)日：2010-05-18

申请号：US11980173

申请日：2007-10-30

申请人： Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

发明人： Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

IPC分类号： H04N5/222 ,  H04N5/228 ,  H03M1/12 ,  H03M1/38

CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/12 ,  H04N5/232 ,  H04N5/23245

摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低 预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。 单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式 水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

公开(公告)号：US07522193B2

公开(公告)日：2009-04-21

申请号：US10862488

申请日：2004-06-07

申请人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

发明人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC分类号： H04N5/235 ,  H04N5/228 ,  H04N5/217

CPC分类号： H04N5/2352

摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US06686957B1

公开(公告)日：2004-02-03

申请号：US09282524

申请日：1999-03-31

申请人： Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

发明人： Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

IPC分类号： H04N5228

CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/12 ,  H04N5/232 ,  H04N5/23245

摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低 预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC），以及耦合到所述ADC的增益电路。 单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式 水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

公开(公告)号：US06285536B1

公开(公告)日：2001-09-04

申请号：US09433812

申请日：1999-11-03

申请人： Douglas R. Holberg ,  Nadi R. Itani ,  David R. Welland

发明人： Douglas R. Holberg ,  Nadi R. Itani ,  David R. Welland

IPC分类号： H02H900

CPC分类号： H01L27/0251 ,  H01L27/0248

摘要： A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate, transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.

摘要翻译： 高压输入焊盘和接受静电放电（ESD）浪涌而不损坏输入半导体放大器的方法。 保护系统包括提供ESD保护的金属栅极，晶体管和n阱电阻。 通过将输入双极结晶体管连接到放大器的负输入连接，进一步提供与放大器耦合的大电压的保护。 负极电流被引导到地，其阳极接地二极管在其阴极处连接到放大器的负输入连接。

公开(公告)号：US07304679B1

公开(公告)日：2007-12-04

申请号：US10742170

申请日：2003-12-19

申请人： Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

发明人： Sandra M. Johnson ,  Douglas R. Holberg ,  Nadi R. Itani

IPC分类号： H04N5/222 ,  H04N5/235 ,  H04N5/20 ,  H03M1/12

CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/12 ,  H04N5/232 ,  H04N5/23245

摘要： A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.

摘要翻译： 用于电荷耦合器件（CCD）或CMOS成像系统的处理系统包括用于从成像器接收数据的相关双样本（CDS）电路，具有可选电流电平的放大器的可变增益放大器（VGA），以使数据分辨率降低 预览显示器，具有可选择的窄位宽输出并耦合到所述VGA电路的低功率模式模数转换器（ADC）以及耦合到所述ADC的增益电路。 单芯片低功耗模拟前端以第一电流电平以13位，12位或10位格式生成数字化CCD数据，并以第二个电流产生9位，8位或6位格式 水平。 VGA放大器包括对称的子电路，它们独立地可启动，以分别在单独的预览屏幕上实现静态图像捕获操作和视频预览的全部或者简化的数据分辨率级别。

公开(公告)号：US07589766B2

公开(公告)日：2009-09-15

申请号：US10659472

申请日：2003-09-10

申请人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

发明人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC分类号： H04N5/235 ,  H04N5/238

CPC分类号： H04N5/2352 ,  H04N5/243

摘要： A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

摘要翻译： 一种用于电荷耦合器件（CCD）或CMOS成像系统的可选阈值多模增益控制装置和方法，包括一自动增益控制（AGC）电路，其连续地控制所述CCD系统中的增益以产生相互连续的组合目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US06650364B1

公开(公告)日：2003-11-18

申请号：US09075348

申请日：1998-05-08

申请人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

发明人： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC分类号： H04N5235

CPC分类号： H04N5/2352 ,  H04N5/243

摘要： A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

公开(公告)号：US07391452B2

公开(公告)日：2008-06-24

申请号：US10801218

申请日：2004-03-16

申请人： Nadi R. Itani

发明人： Nadi R. Itani

IPC分类号： H04N5/20 ,  H04N5/235 ,  H04N5/228 ,  H03M1/00 ,  H03M1/12

CPC分类号： H03M1/187 ,  H04N5/243

摘要： A gain characteristic correctable dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system correctably extends the dynamic range of the imager device, subject to offsets providing linearity corrections at predetermined trip points, subject to determined offset values, to ensure that there are no discontinuities in the system transfer function.

摘要翻译： 增益特性可校正动态范围增强系统（DRES）从连接到相关双采样（CDS）电路的成像器装置接收输入信号，用于从CCD成像装置接收视频信号。 动态范围增强系统包括可变增益放大器（VGA）和有限位宽模数转换器（ADC），数字化从VGA接收的模拟信号。 ADC的输出被提供给连接到ADC的输出的较宽位移移位器的初始位范围位置。 DRES系统可校正地扩展成像器装置的动态范围，经受偏移量，在预定的跳变点提供线性校正，以确定偏移值，以确保系统传递功能中不存在不连续性。