公开(公告)号：US20090182949A1

公开(公告)日：2009-07-16

申请号：US12382449

申请日：2009-03-17

Applicant: Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

Inventor： Florent Begon ,  Philippe Luc ,  Elodie Charra ,  Nicolas Chaussade

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0859 ,  Y02D10/13

Abstract: A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2) transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.

Abstract translation: 一种方法和数据处理装置，包括具有多个数据条目的高速缓存; 驱逐缓冲器，包括信息部分和数据部分; 以及驱逐逻辑，用于将与所述多个数据条目中的第一数据条目相关联的信息从所述高速缓存传送到所述信息部分，并且参考所述信息来确定所述多个数据条目中的第一条数据条目是否应通过检查被写入存储器 信息。 如果确定数据输入应被写入存储器，驱逐逻辑（1）将信息从驱逐缓冲器传送到与存储器耦合的总线，（2）传送多个数据条目中的第一个的数据 从高速缓存到驱逐缓冲器的数据部分，（3）将与多个数据条目中的第二数据条目相关联的信息从高速缓存传送到驱逐缓冲器的关联部分，使得由驱逐的数据部分存储的数据 缓冲器对应于多个数据条目中的第一个，并且由驱逐缓冲器的数据部分存储的信息对应于多个数据条目中的第二数据条目，并且（4）传送由驱逐缓冲器的数据部分存储的数据 到公共汽车 这种方法提供了一种低功耗，高性能的处理驱逐要求的技术。

公开(公告)号：US07305534B2

公开(公告)日：2007-12-04

申请号：US10714561

申请日：2003-11-17

Applicant: Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell ,  Nicolas Chaussade ,  Peter Guy Middleton

Inventor： Simon Charles Watt ,  Lionel Belnet ,  David Hennah Mansell ,  Nicolas Chaussade ,  Peter Guy Middleton

IPC: G06F12/00

CPC classification number: G06F12/1491 ,  G06F21/6218 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2141 ,  G06F2221/2149

Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the present invention, the data processing apparatus further comprises partition checking logic coupled to the device bus and operable whenever the memory access request as issued by the device pertains to the non-secure domain, to detect if the memory access request is seeking to access the secure memory and upon such detection to prevent the access specified by that memory request. This approach significantly improves the security of data contained within a secure portion of memory.

Abstract translation: 本发明提供一种用于控制对存储器的访问的数据处理装置和方法。 数据处理装置具有安全域和非安全域，在安全域中，数据处理装置具有对非安全域中不可访问的安全数据的访问。 数据处理装置包括经由设备总线耦合到存储器的设备，并且当设备需要存储器中的数据项时，可以向设备总线发出存储器访问请求，该存储器访问请求涉及安全域或 非安全域。 存储器可操作以存储设备所需的数据，并且包含用于存储安全数据的安全存储器和用于存储非安全数据的非安全存储器。 根据本发明，数据处理装置还包括耦合到设备总线的分区检查逻辑，每当由设备发布的存储器访问请求与非安全域相关时，可操作，以检测存储器访问请求是否正在寻找 以访问安全存储器并且在这种检测时防止由该存储器请求指定的访问。 这种方法显着提高了包含在存储器安全部分内的数据的安全性。

公开(公告)号：US07124274B2

公开(公告)日：2006-10-17

申请号：US10714560

申请日：2003-11-17

Applicant: Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Michael Robert Nonweiler

Inventor： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Michael Robert Nonweiler

IPC: G06F12/00

CPC classification number: G06F12/145 ,  G06F9/4812 ,  G06F12/1009 ,  G06F12/1027 ,  G06F21/74 ,  G06F2209/481

Abstract: An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.

Abstract translation: 一种用于处理数据的装置，所述装置包括：可以多种模式操作的处理器和安全域或非安全域，所述安全域或非安全域包括作为安全域中的模式的至少一个安全模式; 并且至少一个非安全模式是非安全域中的模式。 当处理器以安全模式执行程序时，程序可以访问当处理器以非安全模式运行时无法访问的安全数据。 处理器还包括分别在非安全和安全域中操作的非安全转换表基地址寄存器和安全转换表基地址寄存器，以指示存储非安全或安全域存储器映射数据的存储器区域 定义如何将虚拟地址转换为非安全或安全域中的物理地址。

公开(公告)号：US07117284B2

公开(公告)日：2006-10-03

申请号：US10714562

申请日：2003-11-17

Applicant: Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

Inventor： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

IPC: G06F13/24

CPC classification number: G06F9/4812

Abstract: A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.

Abstract translation: 数据处理装置可以以多种模式操作，也可以在安全域或非安全域中操作。 当在安全域内以安全模式操作时，程序可以访问当处理器以非安全模式操作时无法访问的安全数据。 提供向量中断控制器以响应于发生除了条件而产生异常处理程序地址。 向量中断控制器是可编程的，参数指定每个异常情况是否应触发安全或非安全域中的异常处理程序，如果在适当的域中发生异常，则使用异常处理程序地址。 向量中断控制器还包括指定域切换异常处理程序地址的参数，以便在处理器不在适当域中时发生异常情况时使用。

公开(公告)号：US20120066481A1

公开(公告)日：2012-03-15

申请号：US12923320

申请日：2010-09-14

Applicant: Nicolas Chaussade ,  Rémi Teyssier

Inventor： Nicolas Chaussade ,  Rémi Teyssier

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3861

Abstract: A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a multiple operation instruction, in response to which multiple data processing operations are performed. The data processing apparatus comprises two or more data processing units configured to perform the data processing operations and an instruction arbitration unit configured to perform sub-division of a multiple operation instruction into a plurality of sub-instructions and to perform allocation of the plurality of sub-instructions amongst the two or more data processing units, wherein each sub-instruction is arranged to cause one of the two or more data processing units to perform at least one data processing operation of the multiple data processing operations. The instruction arbitration unit is configured to perform the sub-division and the allocation dynamically in dependence on a current availability of a resource for each of the two or more data processing units, enabling more efficient usage of the resources of each of the data processing units to be made.

Abstract translation: 提供了一种数据处理装置和方法。 数据处理装置被配置为响应于包括多个操作指令的数据处理指令执行数据处理操作，响应于执行多个数据处理操作。 该数据处理装置包括：两个以上的数据处理单元，被配置为执行数据处理操作;以及指令仲裁单元，被配置为执行多个操作指令的分割为多个子指令，并执行多个子指令的分配 - 所述两个或更多个数据处理单元中的指示，其中每个子指令被布置成使所述两个或更多个数据处理单元中的一个执行所述多个数据处理操作的至少一个数据处理操作。 指令仲裁单元被配置为根据两个或多个数据处理单元中的每一个的资源的当前可用性来动态地执行子划分和分配，使得能够更有效地使用每个数据处理单元的资源 被制造。

公开(公告)号：US20090320048A1

公开(公告)日：2009-12-24

申请号：US10714482

申请日：2003-11-17

Applicant: Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Dominic Hugo Symes

Inventor： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Dominic Hugo Symes

IPC: G06F9/46 ,  G06F9/44

CPC classification number: G06F9/4812 ,  G06F9/526

Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.

Abstract translation: 处理器可以利用两个可以进行呼叫的操作系统（非安全的，安全的）。 为了使第二操作系统能够跟踪由第一操作系统进行的任务切换，每次对第二操作系统进行呼叫时，该呼叫包括标识符，以便能够在第一操作系统上执行的任务之间进行区分， 那个电话是做的。 标识符可以是呼叫标识符和/或目标线程标识符，并且可以包括其他参数。

公开(公告)号：US07600077B2

公开(公告)日：2009-10-06

申请号：US11651620

申请日：2007-01-10

Applicant: Philippe Luc ,  Florent Begon ,  Elodie Charra ,  Nicolas Chaussade

Inventor： Philippe Luc ,  Florent Begon ,  Elodie Charra ,  Nicolas Chaussade

IPC: G06F13/00

CPC classification number: G06F12/0804 ,  G06F12/0897 ,  G06F12/1027

Abstract: Cache circuitry, a data processing apparatus including such cache circuitry, and a method of handling write requests within cache circuitry, are provided. The cache circuitry has a plurality of slots, with each slot arranged to store attributes associated with a pending access request. A record of identifiers that are available to associate with pending access requests is maintained, and control circuitry is responsive to an access request issued by a device to accept that access request as a pending access request by allocating one of the slots to that access request, obtaining one of said identifiers from the record to associate with that access request, and causing the attributes associated with that access request to be stored in the allocated slot along with the obtained identifier. A check procedure is performed to determine, for each pending access request, whether that access request is allowed to proceed. For a speculative pending write access request that is determined to be allowed to proceed, the attributes associated with that access request and the identifier associated with that access request are transferred from the allocated slot to a write entry within a write access buffer, after which the allocated slot is freed for allocation to a subsequent access request. When a speculative confirmed signal is then received from the device specifying that identifier, the write access buffer outputs the attributes from the write entry to store circuitry used to complete the access request. This provides a very efficient mechanism for handling speculative write accesses within a cache.

Abstract translation: 提供了缓存电路，包括这种高速缓存电路的数据处理设备，以及处理高速缓存电路内的写请求的方法。 高速缓存电路具有多个时隙，每个时隙被布置成存储与待处理的接入请求相关联的属性。 维持可用于与未决访问请求相关联的标识符的记录，并且控制电路响应于由设备发出的访问请求，以将该访问请求作为未决访问请求来分配其中一个时隙给该访问请求， 从所述记录中获取所述标识符之一以与所述访问请求相关联，并且将与所述访问请求相关联的属性与所获得的标识符一起存储在所分配的时隙中。 执行检查过程，以确定对于每个未决访问请求，是否允许该访问请求继续进行。 对于被确定为允许继续进行的推测性待决写入访问请求，与该访问请求相关联的属性和与该访问请求相关联的标识符从分配的时隙转移到写访问缓冲器内的写入条目，之后 分配的时隙被释放以分配给后续的访问请求。 当从指定该标识符的设备接收到推测确认的信号时，写入访问缓冲器从写入条目输出属性以存储用于完成访问请求的存储电路。 这提供了一种处理高速缓存中的推测性写入访问的非常有效的机制。

公开(公告)号：US07552285B2

公开(公告)日：2009-06-23

申请号：US11512396

申请日：2006-08-30

Applicant: Florent Begon ,  Nicolas Chaussade ,  Elodie Charra ,  Philippe Luc

Inventor： Florent Begon ,  Nicolas Chaussade ,  Elodie Charra ,  Philippe Luc

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0859

Abstract: A line fill method, line fill unit and data processing apparatus are disclosed. The line fill method, comprises the steps of: a) associating a line fill buffer with a unique identifier; b) initiating a line fill request to provide said line fill buffer with line fill data, said line fill request having said unique identifier associated therewith; and c) in the event that said line fill buffer is filled with said line fill data prior to said line fill data having been returned in response to said line fill request, associating said line fill buffer with a different unique identifier to enable a subsequent line fill request to be initiated. By enabling the line fill buffer to be associated with different unique identifiers, the line fill buffer can initiate a new request despite the previous request not having been completed without there being any concern that the returned data may be misallocated. This enables multiple line fill requests to be simultaneously pending and subsequent line fill requests to be initiated whilst previous line fill requests are outstanding. Accordingly, subsequent line fill requests may be initiated earlier than would have been possible had the line fill buffer had to wait for all of the line fill data associated with each line fill request to be returned.

Abstract translation: 公开了线填充方法，线填充单元和数据处理装置。 行填充方法包括以下步骤：a）将行填充缓冲器与唯一标识符相关联; b）启动线填充请求以向所述线填充缓冲器提供线填充数据，所述线填充请求具有与其相关联的所述唯一标识符; 以及c）在所述行填充缓冲器在所述行填充数据已被响应于所述行填充请求返回之前，用所述行填充数据填充的情况下，将所述行填充缓冲器与不同的唯一标识符相关联以使得后续行 填写请求启动。 通过使行填充缓冲区能够与不同的唯一标识符相关联，即使先前的请求未被完成，行填充缓冲器也可以启动新的请求，而不用担心返回的数据可能被错位。 这使得多个线填充请求同时处于待决状态，并且在先前的行填充请求未完成时启动后续的行填充请求。 因此，如果行填充缓冲器必须等待与每个行填充请求相关联的所有行填充数据被返回，则可以提前开始后续的行填充请求。

公开(公告)号：US07487367B2

公开(公告)日：2009-02-03

申请号：US10714521

申请日：2003-11-17

Applicant: Lionel Belnet ,  Nicolas Chaussade ,  Simon Charles Watt ,  Peter Guy Middleton

Inventor： Lionel Belnet ,  Nicolas Chaussade ,  Simon Charles Watt ,  Peter Guy Middleton

IPC: H04L9/06 ,  G06F12/00

CPC classification number: G06F12/1491

Abstract: The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data. The memory further contains a non-secure table and a secure table, the non-secure table being within the non-secure memory and arranged to contain for each of a number of first memory regions an associated descriptor, and the secure table being within the secure memory and arranged to contain for each of a number of second memory regions an associated descriptor. When access to an item of data in the memory is required by the processor, the processor issues a memory access request, and a memory management unit is provided to perform one or more predetermined access control functions to control issuance of the memory access request to the memory. The memory management unit comprises an internal storage unit operable to store descriptors retrieved by the memory management unit from either the non-secure table or the secure table, and in accordance with the present invention the internal storage unit comprises a flag associated with each descriptor stored within the internal storage unit to identify whether that descriptor is from the non-secure table or the secure table. By this approach, when the processor is operating in a non-secure mode, the memory management unit is operable to perform the predetermined access control functions for the memory access request with reference to access control information derived from the descriptors in the internal storage unit retrieved from the non-secure table. In contrast, when the processor is operating in a secure mode, the memory management unit is operable to perform the predetermined access control functions for the memory access request with reference to access control information derived from the descriptors in the internal storage unit retrieved from the secure table. This approach enables different descriptors to be used for the control of accesses to memory in either the secure domain or the non-secure domain, whilst enabling such different descriptors to co-exist within the memory management unit's internal storage unit, thereby avoiding the requirement to flush the contents of such an internal storage unit when the operation of the processor changes from the secure domain to the non-secure domain, or vice versa.

公开(公告)号：US20080148029A1

公开(公告)日：2008-06-19

申请号：US11637948

申请日：2006-12-13

Applicant: Philippe Luc ,  Norbert Bernard Eugene Lataille ,  Florent Begon ,  Nicolas Chaussade

Inventor： Philippe Luc ,  Norbert Bernard Eugene Lataille ,  Florent Begon ,  Nicolas Chaussade

IPC: G06F9/30

CPC classification number: G06F9/30025 ,  G06F9/30032 ,  G06F9/3824

Abstract: A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided within the data processing apparatus for receiving a block of data containing at least one data value, and for converting each data value in the block from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first predetermined size, in order to produce re-ordered data. Further, second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first predetermined size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format. The swizzle circuitry is responsive to an indication that the at least one data value is of the first predetermined size to output the re-ordered data produced by the first swizzle circuitry, whereas otherwise the swizzle circuitry outputs the data produced by the second swizzle circuitry. This can reduce the complexity of swizzle circuitry provided on a critical path, by optimising the swizzle circuitry to handle endian conversion for data values of the first predetermined size, at the expense of data values that are of other sizes requiring more time for the endian conversion operation to be completed.

Abstract translation: 提供了一种数据处理装置和方法，用于将数据值从第一端格式转换成第二端格式。 在数据处理装置内设置有旋转电路，用于接收包含至少一个数据值的数据块，并将该块中的每个数据值从第一端格式转换为第二端格式。 所述交换电路包括用于对所述数据块执行重新排序操作的第一交换电路，其假设其中包含的所述至少一个数据值具有第一预定大小，以便产生重新排序的数据。 此外，提供了第二旋转电路，其响应于至少一个数据值具有不同于第一预定大小的大小的指示，以对已重新排序的数据执行额外的重新排序操作，其中考虑到 所述至少一个数据值以将每个数据值转换为第二端格式。 交换电路响应于至少一个数据值具有第一预定大小的指示，以输出由第一开关电路产生的重新排序的数据，而否则该转换电路输出由第二开关电路产生的数据。 这可以降低在关键路径上提供的交换电路的复杂性，通过优化旋转电路以处理第一预定大小的数据值的端序转换，代价是需要更多时间用于端序转换的其他大小的数据值 操作完成。