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    Predicting branch instructions
    2.
    发明申请
    Predicting branch instructions 有权
    预测分支指令

    公开(公告)号：US20080148028A1

    公开(公告)日：2008-06-19

    申请号：US11641120

    申请日：2006-12-19

    申请人： Gilles Eric Grandou ,  Stephane Eric Sebastien Brochier ,  Louis-Marie Vincent Mouton

    发明人： Gilles Eric Grandou ,  Stephane Eric Sebastien Brochier ,  Louis-Marie Vincent Mouton

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3806

    摘要： A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instruction; and said data processing apparatus is operable over a period of time to access predetermined information corresponding to more instructions within said branch target cache than instructions it prefetches from said memory such that said accesses to said branch target cache develop an advance in said instruction stream with respect to accesses to said memory; and said prefetch unit is operable to access said data store and to determine if there is data corresponding to an instruction within said data store that indicates that said instruction specifies a branch operation that will be taken and will cause a change in instruction flow.

    摘要翻译： 公开了一种数据处理装置，包括：处理器，用于处理解码指令流; 预取单元，用于在将所述指令流发送到所述处理器之前从存储器中取出指令流内的指令; 分支预测逻辑，用于预测分支指令的行为; 分支目标缓存，用于存储关于由所述处理器执行的分支操作的预定信息，所述预定信息包括：用于指定分支操作的指令的识别数据和与是否采用所述分支有关的数据; 其中所述数据处理装置可操作以访问所述分支目标高速缓存并且确定是否存在与存储在所述分支目标高速缓存内的所述指令流内的指令相对应的数据，以及是否输出所述数据; 所述数据处理装置还包括：数据存储器，用于存储指示分支指令的行为的数据; 并且所述数据处理装置在一段时间内可操作以访问与所述分支目标高速缓存器内的更多指令相对应的预定信息，而不是从其从所述存储器预取的指令，使得对所述分支目标高速缓存的所述访问在所述指令流中相对于 访问所述存储器; 并且所述预取单元可操作以访问所述数据存储并且确定是否存在与所述数据存储器内的指令相对应的数据，其指示所述指令指定将被采用的分支操作，并且将导致指令流程的改变。

    Exception handling control in a secure processing system
    3.
    发明授权
    Exception handling control in a secure processing system 有权
    安全处理系统中的异常处理控制

    公开(公告)号：US07383587B2

    公开(公告)日：2008-06-03

    申请号：US10714565

    申请日：2003-11-17

    申请人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier

    发明人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier

    IPC分类号： G06F17/30

    CPC分类号： G06F21/74 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2009/45587

    摘要： A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is executing a program in a secure mode and that program has access to secure data which is not accessible when the processor is operating in a non-secure mode, the processor is responsive to exception conditions for triggering exception processing. Specifically, the processor is responsive to a parameter specifying which of the exceptions should be handled by a secure mode exception handler executing in a secure mode and which should be handled by an exception handler executing in a mode within a current one of the secure domain and the non-secure domain when that exception occurs.

    摘要翻译： 数据处理系统包括可以以多种模式并且在安全域或非安全域中操作的处理器。 至少一个安全模式是安全域中的模式，并且至少一个非安全模式是非安全域中的模式。 当处理器以安全模式执行程序并且该程序可以访问当处理器以非安全模式操作时不可访问的安全数据时，处理器响应用于触发异常处理的异常条件。 具体地说，处理器响应于指定哪个异常应由安全模式执行的安全模式异常处理程序处理的参数，并且应该由在当前安全域内的模式中执行的异常处理程序处理， 发生异常时的非安全域。

    Cache accessing using muTAGs
    4.
    发明申请
    Cache accessing using muTAGs 有权
    使用muTAG缓存访问

    公开(公告)号：US20080114939A1

    公开(公告)日：2008-05-15

    申请号：US11599596

    申请日：2006-11-15

    申请人： Louis-Marie Vincent Mouton ,  Gilles Eric Grandou ,  Stephane Eric Sebastien Brochier

    发明人： Louis-Marie Vincent Mouton ,  Gilles Eric Grandou ,  Stephane Eric Sebastien Brochier

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0895 ,  G06F12/0864 ,  G06F12/1045 ,  Y02D10/13

    摘要： A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one of said plurality of recently accessed cache storage locations and if so to identify a cache way of said cache storage location from data stored in both said data store and said table.

    摘要翻译： 数据处理器，可操作用于处理数据，所述数据处理器包括：分组为多个高速缓存路径并可操作以存储由所述数据处理器处理的数据的集合相关高速缓存; 缓冲器，用于将包括多个虚拟地址页面的表的表存储到所述数据处理器的物理地址页; 数据存储器，其包括多个数据条目，每个数据条目可操作以存储用于识别多个最近高速缓存访​​问中的每一个的存储器位置的地址的数据，所述多个数据条目中的每一个包括指示地址空间中的页面的页面索引 ，指示所述页面内的位置的偏移数据和标识由所述高速缓存访​​问访问的高速缓存存储位置的高速缓存方式的高速缓存路数据; 其中所述数据处理器可操作以响应于高速缓存访​​问请求，所述高速缓存访​​问请求包括指示访问所述表的存储器位置的虚拟地址和所述数据存储，以确定所述高速缓存访​​问请求是否是所述多个最近访问的缓存存储位置之一，以及 因此从存储在所述数据存储器和所述表中的数据中识别所述高速缓存存储位置的缓存方式。

    Data processing apparatus
    8.
    发明授权
    Data processing apparatus 有权
    数据处理装置

    公开(公告)号：US07840001B2

    公开(公告)日：2010-11-23

    申请号：US11266474

    申请日：2005-11-04

    申请人： Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  Simon Andrew Ford

    发明人： Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  Simon Andrew Ford

    IPC分类号： H04K1/06

    CPC分类号： G06F9/3836 ,  G06F9/3855

    摘要： Data processing apparatus and methods are provided. One data processing apparatus comprises: a plurality of pipelined stages, each of the plurality pipelined stages being operable in each processing cycle to receive a group of data elements from an earlier pipelined stage; permute logic operable to buffer ‘n’ of the groups of data elements over a corresponding ‘n’ processing cycles thereby creating a bubble within pipelined stages, and forwarding logic operable, once the ‘n’ of the groups of data elements have been buffered by the permute logic, to forward permuted groups of data elements comprising the data elements reordered by the permute logic to fill the bubble within the pipelined stages. By forwarding the data elements to fill the bubble an improved throughput can be achieved and since a constant stream of data can be transformed without the need to increase the number of input or output registers required to support the permute logic, the need to duplicate the permute logic or the need to introduce any additional storage elements.

    摘要翻译： 提供数据处理装置和方法。 一个数据处理装置包括：多个流水线级，多个流水线阶段中的每一个在每个处理周期中可操作以从较早的流水线阶段接收一组数据元素; 置换逻辑可操作以在相应的“n”个处理周期中缓冲数据组组中的“n”，从而在流水线阶段内产生气泡，一旦数据组组中的“n”已被 置换逻辑，以将包括由置换逻辑重新排序的数据元素的数据元素组置换以填充流水线阶段内的气泡。 通过转发数据元素以填充气泡，可以实现改进的吞吐量，并且由于可以变换恒定的数据流，而不需要增加支持置换逻辑所需的输入或输出寄存器的数量，所以需要重复置换 逻辑或需要引入任何额外的存储元件。

    Accessing branch predictions ahead of instruction fetching
    9.
    发明授权
    Accessing branch predictions ahead of instruction fetching 有权
    在提取指令之前访问分支预测

    公开(公告)号：US07783869B2

    公开(公告)日：2010-08-24

    申请号：US11641120

    申请日：2006-12-19

    申请人： Gilles Eric Grandou ,  Stephane Eric Sebastien Brochier ,  Louis-Marie Vincent Mouton

    发明人： Gilles Eric Grandou ,  Stephane Eric Sebastien Brochier ,  Louis-Marie Vincent Mouton

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3844 ,  G06F9/3806

    摘要： A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said processor; branch prediction logic operable to predict a behaviour of a branch instruction; a branch target cache for storing predetermined information about branch operations executed by said processor, said predetermined information comprising: identification data for an instruction specifying a branch operation and data relating to whether said branch is taken or not; wherein said data processing apparatus is operable to access said branch target cache and to determine if there is data corresponding to instructions within said stream of instructions stored within said branch target cache and if there is to output said data; said data processing apparatus further comprising: a data store operable to store data indicative of a behaviour of a branch instruction; and said data processing apparatus is operable over a period of time to access predetermined information corresponding to more instructions within said branch target cache than instructions it prefetches from said memory such that said accesses to said branch target cache develop an advance in said instruction stream with respect to accesses to said memory; and said prefetch unit is operable to access said data store and to determine if there is data corresponding to an instruction within said data store that indicates that said instruction specifies a branch operation that will be taken and will cause a change in instruction flow.

    摘要翻译： 公开了一种数据处理装置，包括：处理器，用于处理解码指令流; 预取单元，用于在将所述指令流发送到所述处理器之前从存储器中取出指令流内的指令; 分支预测逻辑，用于预测分支指令的行为; 分支目标缓存，用于存储关于由所述处理器执行的分支操作的预定信息，所述预定信息包括：用于指定分支操作的指令的识别数据和与是否采用所述分支有关的数据; 其中所述数据处理装置可操作以访问所述分支目标高速缓存并且确定是否存在与存储在所述分支目标高速缓存内的所述指令流内的指令相对应的数据，以及是否输出所述数据; 所述数据处理装置还包括：数据存储器，用于存储指示分支指令的行为的数据; 并且所述数据处理装置在一段时间内可操作以访问与所述分支目标高速缓存器内的更多指令相对应的预定信息，而不是从其从所述存储器预取的指令，使得对所述分支目标高速缓存的所述访问在所述指令流中相对于 访问所述存储器; 并且所述预取单元可操作以访问所述数据存储并且确定是否存在与所述数据存储器内的指令相对应的数据，其指示所述指令指定将被采用的分支操作，并且将导致指令流程的改变。