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    Function control for a processor
    4.
    发明授权
    Function control for a processor 有权
    一个处理器的功能控制

    公开(公告)号：US07231476B2

    公开(公告)日：2007-06-12

    申请号：US10714480

    申请日：2003-11-17

    Applicant: Simon Charles Watt ,  Luc Orion ,  Nicolas Chaussade

    Inventor： Simon Charles Watt ,  Luc Orion ,  Nicolas Chaussade

    IPC: G06F11/30

    CPC classification number: G06F9/468

    Abstract: A processor operable to perform a plurality of functions, the processor comprising: an input port; a storage element operable to receive and to store an input signal input via the input port, the input signal comprising at least one control value; control logic operable to control at least one of the functions of the processor in dependence on the at least one control value; and access logic operable to receive an access control signal and to disable access via the input port to the at least one control value stored in the storage element in dependence upon the access control signal.

    Abstract translation: 一种可操作以执行多个功能的处理器，所述处理器包括：输入端口; 存储元件，其可操作以接收并存储经由所述输入端口输入的输入信号，所述输入信号包括至少一个控制值; 控制逻辑可操作以根据所述至少一个控制值来控制所述处理器的功能中的至少一个; 以及访问逻辑，其可操作以接收访问控制信号，并且根据访问控制信号禁止通过输入端口访问存储在存储元件中的至少一个控制值。

    Data transfer between a master and slave
    5.
    发明授权
    Data transfer between a master and slave 有权
    主机与从机之间的数据传输

    公开(公告)号：US09378175B2

    公开(公告)日：2016-06-28

    申请号：US11979361

    申请日：2007-11-01

    Applicant: Nicolas Chaussade ,  Pierre Michel Broyer ,  Phillipe Luc

    Inventor： Nicolas Chaussade ,  Pierre Michel Broyer ,  Phillipe Luc

    IPC: G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/42

    CPC classification number: G06F13/4291

    Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configured to output signals that are different to each other.

    Abstract translation: 一种数据处理装置，包括至少一个启动器，其可操作以经由总线与至少一个接收者通信; 所述至少一个启动器包括用于向所述总线发送数据的输出端口和用于从所述总线接收数据的输入端口; 所述数据处理装置还包括启动器时钟信号发生器，启动器输出使能信号发生器和启动器输入使能信号发生器，所述启动器由所述启动器时钟信号计时; 所述输出端口由所述启动器输出使能信号计时，使得所述输出端口可操作以响应于具有第一预定电平的所述启动器输出使能信号而将数据断言在所述总线上的写通道，并且所述输入端口可操作以锁存数据 响应于所述启动器输入使能信号具有第二预定电平，在所述总线上的读通道上接收; 其中所述启动器输出使能信号发生器和启动器输入使能信号发生器被配置为输出彼此不同的信号。

    Managing the storage of data in coherent data stores
    6.
    发明授权
    Managing the storage of data in coherent data stores 有权
    管理连贯数据存储中的数据存储

    公开(公告)号：US09164910B2

    公开(公告)日：2015-10-20

    申请号：US12071504

    申请日：2008-02-21

    Applicant: Nicolas Chaussade ,  Stephane Eric Sebastien Brochier

    Inventor： Nicolas Chaussade ,  Stephane Eric Sebastien Brochier

    IPC: G06F12/08

    CPC classification number: G06F12/0835 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1016

    Abstract: A data processing apparatus comprises: at least one processor; having a private cache, a shared cache for storing data processed by the processor and by a further device, and coherency control circuitry. The coherency control circuitry is responsive to a write request from the further device to determine if data related to an address targeted by the write request is stored in the private cache, and if it is, forcing an eviction of the stored data from the private cache to the shared cache prior to perform the write to the shared cache. The data is stored in the private cache in conjunction with an indicator indicating if the stored data is consistent with data stored in a corresponding address in a further data store, and the stored data is evicted whether the stored data is indicated as being consistent or inconsistent.

    Abstract translation: 一种数据处理装置，包括：至少一个处理器; 具有专用高速缓存，用于存储由处理器和另一设备处理的数据的共享高速缓存以及一致性控制电路。 相关性控制电路响应于来自另一设备的写入请求，以确定与由写入请求所针对的地址有关的数据是否存储在专用高速缓存中，并且如果是，强制从专用高速缓存中移出所存储的数据 在对共享缓存执行写入之前到共享缓存。 数据与指示存储的数据是否与存储在另一个数据存储器中的对应地址中的数据一致的指示符存储在专用高速缓存中，并且所存储的数据被驱逐是否所存储的数据被表示为一致或不一致 。

    Data processing apparatus and method using checkpointing
    7.
    发明申请
    Data processing apparatus and method using checkpointing 有权
    数据处理装置和方法使用检查点

    公开(公告)号：US20120036340A1

    公开(公告)日：2012-02-09

    申请号：US12805567

    申请日：2010-08-05

    Applicant: Nicolas Chaussade ,  Florent Begon ,  Mélanie Emanuelle Lucie Teyssier ,  Rémi Teyssier ,  Jocelyn Francois Orion Jaubert

    Inventor： Nicolas Chaussade ,  Florent Begon ,  Mélanie Emanuelle Lucie Teyssier ,  Rémi Teyssier ,  Jocelyn Francois Orion Jaubert

    IPC: G06F9/312

    CPC classification number: G06F9/3861 ,  G06F9/30145 ,  G06F9/3842 ,  G06F9/3863

    Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction.

    Abstract translation: 提供数据处理装置和数据处理方法。 该数据处理装置包括被配置为执行程序指令序列的执行电路。 检查点电路被配置为识别程序指令序列中的预定类型的指令的实例，并且存储与该实例相关联的检查点信息。 检查点信息在执行预定类型的指令的该实例之前识别数据处理装置的状态，其中预定类型的指令具有期望的长完成延迟。 如果执行电路由于发生预定事件而没有完成预定类型的指令的实例的执行，则数据处理装置被配置为参照检查点信息恢复数据处理装置的状态，使得 然后，执行电路被配置为在预定类型的指令的那个情况下重新开始执行程序指令的序列。

    Exception types within a secure processing system
    8.
    发明授权
    Exception types within a secure processing system 有权
    安全处理系统中的异常类型

    公开(公告)号：US07661105B2

    公开(公告)日：2010-02-09

    申请号：US10714519

    申请日：2003-11-17

    Applicant: Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier

    Inventor： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier

    IPC: G06F9/46

    CPC classification number: G06F21/74 ,  G06F9/4812 ,  G06F2209/481

    Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

    Abstract translation: 一种用于处理数据的装置包括可以以多种模式操作的处理器，包括至少一种安全模式，即安全域中的模式，以及至少一种非安全模式是非安全域中的模式。 当处理器以安全模式执行程序时，程序可以访问当处理器以非安全模式运行时无法访问的安全数据。 处理器响应于一个或多个异常条件，以使用异常处理程序触发异常处理。 处理器可操作以依赖于处理器是否在安全域或非安全域中操作从多个可能的异常处理程序中选择异常处理程序。

    Managing the storage of data in coherent data stores
    9.
    发明申请
    Managing the storage of data in coherent data stores 有权
    管理连贯数据存储中的数据存储

    公开(公告)号：US20090216957A1

    公开(公告)日：2009-08-27

    申请号：US12071504

    申请日：2008-02-21

    Applicant: Nicolas Chaussade ,  Stephane Eric Sebastien Brochier

    Inventor： Nicolas Chaussade ,  Stephane Eric Sebastien Brochier

    IPC: G06F12/08

    CPC classification number: G06F12/0835 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1016

    Abstract: A data processing apparatus is disclosed that comprises: at least one processor; at least one data store for storing data processed by said at least one processor; a shared data store for storing data processed by said at least one processor and at least one further device; and coherency control circuitry responsive to a write request from said at least one further device to determine if data related to an address targeted by said write request is stored in said at least one data store, and if it is forcing an eviction of said stored data from said at least one data store to said shared data store prior to performing said write to said shared data store; wherein said data is stored in said at least one data store in conjunction with an indicator indicating if said stored data is consistent with data stored in a corresponding address in a further data store, and said stored data is evicted whether said stored data is indicated as being consistent or inconsistent.

    Abstract translation: 公开了一种数据处理装置，包括：至少一个处理器; 用于存储由所述至少一个处理器处理的数据的至少一个数据存储器; 共享数据存储器，用于存储由所述至少一个处理器处理的数据和至少一个另外的设备; 以及响应于来自所述至少一个另外的设备的写请求的相关性控制电路，以确定与所述写请求所针对的地址相关的数据是否存储在所述至少一个数据存储器中，并且如果它强制驱逐所述存储的数据 在对所述共享数据存储器执行所述写入之前，从所述至少一个数据存储器到所述共享数据存储器; 其中所述数据与指示所述存储的数据是否与存储在另一个数据存储器中的对应地址中的数据一致的指示符存储在所述至少一个数据存储器中，并且所述存储的数据被驱逐是否所述存储的数据被指示为 一致或不一致。

    Data transfer between devices within an integrated circuit
    10.
    发明申请
    Data transfer between devices within an integrated circuit 有权
    集成电路内的器件之间的数据传输

    公开(公告)号：US20090210595A1

    公开(公告)日：2009-08-20

    申请号：US12320718

    申请日：2009-02-03

    Applicant: Nicolas Chaussade

    Inventor： Nicolas Chaussade

    IPC: G06F13/40

    CPC classification number: G06F13/4022 ,  H03M7/46

    Abstract: An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in place of that repeating data word itself. The receiving device can then form the repeating pattern of data words in response to receipt of the representation. This reduces the bandwidth consumed upon the interconnect 16.

    Abstract translation: 提供了集成电路2，其包括用于经由互连16进行通信的多个设备4,6,8,10,12,14。发送设备18包括表示使用重复数据字的表示的边带信号，代替该重复数据字的表示 重复数据字本身。 然后，响应于接收到表示，接收设备可以形成数据字的重复模式。 这减少了互连16上消耗的带宽。

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