公开(公告)号：US12249995B2

公开(公告)日：2025-03-11

申请号：US18357562

申请日：2023-07-24

Applicant: ROHM CO., LTD.

Inventor： Shinichi Saito

IPC: H03K5/24 ,  H03F3/45 ,  H03K7/02

Abstract: The first stage of the differential interface circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gates of the first transistor and the second transistor are coupled to input terminals, respectively. The third transistor and the fourth transistor are coupled in parallel with the first transistor and the second transistor, respectively. The gate of the third transistor is coupled to the drain of the second transistor, and the gate of the fourth transistor is coupled to the drain of the first transistor.

公开(公告)号：US12241860B2

公开(公告)日：2025-03-04

申请号：US17499991

申请日：2021-10-13

Applicant: ROHM Co., LTD.

Inventor： Yurina Amamoto ,  Shunsuke Akasaka

IPC: G01N27/416 ,  C23F1/02 ,  C23F1/12 ,  G01N1/44 ,  G01N27/407 ,  G01N33/00

Abstract: Provided is a sensor including a substrate that includes a major surface, a sensor part that includes a gas flow path formed of a porous material, and at least one of a heater or a temperature sensor. The heater is capable of heating the sensor part, the temperature sensor is capable of measuring temperature of the sensor part, the sensor part and the at least one of the heater or the temperature sensor are stacked over the major surface, the at least one of the heater or the temperature sensor is an interconnect having forward tapered side surfaces, and the at least one of the heater or the temperature sensor includes a metal interconnect layer, and the forward tapered side surfaces of the interconnect overlap with the gas flow path in plan view of the major surface.

公开(公告)号：US20250072296A1

公开(公告)日：2025-02-27

申请号：US18806480

申请日：2024-08-15

Applicant: ROHM CO., LTD.

Inventor： Sho KAWAKAMI ,  Yasufumi TOYODA

IPC: H10N52/00 ,  H10N52/01

Abstract: The present disclosure provides a Hall element. The Hall element includes: a substrate; a magnetosensitive layer, disposed on a top surface of the substrate; a protective layer, covering the magnetosensitive layer and having an opening exposing a predetermined region of the magnetosensitive layer; an ohmic contact layer, electrically connected to the magnetosensitive layer exposed from the opening, wherein a portion of the ohmic contact layer is in contact with the protective layer around the opening; and a metal layer, disposed on the ohmic contact layer, wherein a portion of the metal layer is in contact with the protective layer around the ohmic contact layer.

公开(公告)号：US20250072088A1

公开(公告)日：2025-02-27

申请号：US18801879

申请日：2024-08-13

Applicant: ROHM CO., LTD.

Inventor： Tomonori KATO

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode on the gate layer, a source electrode, and a drain electrode. The gate layer includes a first gate portion, a second gate portion, and a recess between the first gate portion and the second gate portion. The gate electrode is arranged over both the first gate portion and the second gate portion. The nitride semiconductor device further includes an insulator located in the recess.

公开(公告)号：US20250072012A1

公开(公告)日：2025-02-27

申请号：US18790083

申请日：2024-07-31

Applicant: ROHM CO., LTD.

Inventor： Masanobu TSUJI ,  Yoshizo OSUMI

IPC: H01F27/28 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor device includes: a first chip including a first semiconductor substrate, a first circuit, and a first element insulating layer formed over the first semiconductor substrate; a second chip spaced apart from the first chip in a first direction and including a second semiconductor substrate, a second circuit, and a second element insulating layer formed over the second semiconductor substrate; a sub-mount chip separate from the first and second chips; and a transformer chip disposed over the sub-mount chip and including a transformer through which the first and second circuits transmit signals or power, wherein the transformer chip includes a third semiconductor substrate and a third element insulating layer formed over the third semiconductor substrate, wherein the transformer is embedded in the third element insulating layer, and wherein the sub-mount chip includes a fourth semiconductor substrate and an insulating layer formed over the fourth semiconductor substrate.

公开(公告)号：US20250070103A1

公开(公告)日：2025-02-27

申请号：US18790093

申请日：2024-07-31

Applicant: ROHM CO., LTD.

Inventor： Masanobu TSUJI ,  Yoshizo OSUMI ,  Keiji WADA ,  Bungo TANAKA

IPC: H01L25/16 ,  H01F27/28 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor device includes: a first chip including a first circuit; a second chip disposed to be spaced apart from the first chip in a first direction and including a second circuit; and a transformer chip disposed over the first chip and including a transformer. The first circuit and the second circuit are configured to transmit a signal or power via the transformer. The transformer chip includes: an element insulating layer; and an outer coil and an inner coil disposed as the transformer in the element insulating layer. The inner coil is disposed inside the outer coil so as not to overlap the outer coil when viewed from a thickness direction of the element insulating layer.

公开(公告)号：US20250070076A1

公开(公告)日：2025-02-27

申请号：US18946363

申请日：2024-11-13

Applicant: Rohm Co., Ltd.

Inventor： Hiroaki MATSUBARA

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/065

Abstract: A semiconductor device includes a first wire, a first semiconductor element including an electrode electrically connected to the first wire, and a bump electrically bonded to the electrode. The first wire includes a first bonding portion located at one end and a second bonding portion located at another end. The bump includes a disc portion in contact with the electrode, and a pillar portion protruding from the disc portion in a first direction. The second bonding portion is electrically bonded to the pillar portion. A dimension of the pillar portion in the first direction increases as approaching the first bonding portion.

公开(公告)号：US20250070051A1

公开(公告)日：2025-02-27

申请号：US18943120

申请日：2024-11-11

Applicant: ROHM CO., LTD.

Inventor： Hidetoshi ABE ,  Makoto IKENAGA ,  Kensei TAKAMOTO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.

公开(公告)号：US20250069996A1

公开(公告)日：2025-02-27

申请号：US18943499

申请日：2024-11-11

Applicant: Rohm Co., Ltd.

Inventor： Hiroaki MATSUBARA

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor element, a sealing resin covering the semiconductor element, a terminal electrically connected to the semiconductor element and protruding from the sealing resin in a first direction orthogonal to a thickness direction, and a plating layer located on the terminal. The terminal includes an end surface at a distal end protruding from the sealing resin, a first surface facing a first side in the thickness direction, and a recess recessed from both the end surface and the first surface. The plating layer includes a recess plating section located on at least a portion of the recess.

公开(公告)号：US20250068790A1

公开(公告)日：2025-02-27

申请号：US18812521

申请日：2024-08-22

Applicant: ROHM CO., LTD.

Inventor： Kenji HAMACHI

IPC: G06F30/20 ,  G06F111/10

Abstract: A simulation apparatus comprises a model storage unit storing a motor physical model modeled by a wiring circuit section and a rotation motion equation section, and an abnormal state model obtained by modeling a motor abnormal state; and a model arithmetic unit configured to perform arithmetic processing using the motor physical model. The abnormal state model calculates an abnormal parameter indicating a deviation amount from a normal state, and the abnormal parameter is input to the motor physical model.