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公开(公告)号:US11329040B2
公开(公告)日:2022-05-10
申请号:US16359431
申请日:2019-03-20
Applicant: STMicroelectronics (Tours) SAS
Inventor: Patrick Poveda
IPC: H02H9/00 , H01L27/02 , H01L29/87 , H01L29/66 , H01L23/60 , H01L29/78 , H01L29/788 , H01L23/522 , H01L23/528 , H01L27/06 , H01L29/06 , H01L29/866 , H02H9/04 , H03H11/04
Abstract: An electronic component includes first and second separate semiconductor regions. A third semiconductor region is arranged under and between the first and second semiconductor regions. The first and third semiconductor regions define electrodes of a first diode. The second and third semiconductor regions define electrodes of a second diode. The first diode is an avalanche diode.
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公开(公告)号:US11289391B2
公开(公告)日:2022-03-29
申请号:US16802325
申请日:2020-02-26
Applicant: STMICROELECTRONICS (TOURS) SAS
Inventor: Olivier Ory
IPC: H01L23/31 , H01L21/3205 , H01L21/56 , H01L21/78 , H01L29/861
Abstract: A device comprising a semiconductor substrate, an electrically-conductive layer covering the substrate, and an insulating sheath, the conductive layer being in contact with the insulating sheath on the side opposite to the substrate.
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公开(公告)号:US20220077850A1
公开(公告)日:2022-03-10
申请号:US17466604
申请日:2021-09-03
Applicant: STMicroelectronics (Tours) SAS
Inventor: Romain PICHON , Yannick HAGUE
Abstract: A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.
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公开(公告)号:US11251478B2
公开(公告)日:2022-02-15
申请号:US16372604
申请日:2019-04-02
Applicant: STMicroelectronics (Tours) SAS
Inventor: Vincent Jarry
IPC: H01M2/02 , H01M6/40 , H01M10/04 , H01M2/30 , H01M2/22 , H01M50/10 , H01M50/116 , H01M50/124 , H01M50/528 , H01M50/543
Abstract: An electronic device includes a base substrate, and a plurality of battery substrates constructed from mica and being attached to the base substrate. An aggregate area of the base substrate is greater than an aggregate area of the plurality of battery substrates. The electronic device also includes a plurality of active battery layers, each active battery layer being attached to a different respective battery substrate, with each active battery layer having a smaller area than its corresponding battery substrate. A film is disposed over the plurality of active battery layers and sized such that the film extends beyond each active battery layer to contact each battery substrate, and such that the film extends beyond each battery substrate to contact the base substrate.
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公开(公告)号:US11228239B2
公开(公告)日:2022-01-18
申请号:US16858907
申请日:2020-04-27
Applicant: STMicroelectronics (Tours) SAS , STMicroelectronics LTD
Inventor: Ghafour Benabdelaziz , Laurent Gonthier
Abstract: An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input.
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公开(公告)号:US11150682B2
公开(公告)日:2021-10-19
申请号:US17085493
申请日:2020-10-30
Applicant: STMICROELECTRONICS (TOURS) SAS
Inventor: Kuno Lenz
Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.
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公开(公告)号:US20210135590A1
公开(公告)日:2021-05-06
申请号:US17071193
申请日:2020-10-15
Applicant: STMicroelectronics (Tours) SAS
Inventor: Yannick HAGUE , Romain LAUNOIS
IPC: H02M7/162
Abstract: A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.
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公开(公告)号:US20200321330A1
公开(公告)日:2020-10-08
申请号:US16834329
申请日:2020-03-30
Applicant: STMicroelectronics (Tours) SAS
Inventor: Eric LACONDE , Olivier ORY
IPC: H01L27/02 , H01L29/87 , H01L29/866
Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.
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公开(公告)号:US10797290B2
公开(公告)日:2020-10-06
申请号:US15440683
申请日:2017-02-23
Applicant: STMicroelectronics (Tours) SAS
Inventor: Mohamed Boufnichel , Julien Ladroue
Abstract: Identical planar electronic components are stacked in an assembly. Each component has two contact metallizations positioned on edges of a same surface of the component. The components are stacked along a common axis. Each successive component is rotated about the common axis by a fixed angle. A value of the fixed angle is selected to position, side by side, the contact metallization of one component and the contact metallization of another next component adjacent to each other in the stack. Electrical connections are provided between two adjacent contact metallizations.
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公开(公告)号:US20200280310A1
公开(公告)日:2020-09-03
申请号:US16879561
申请日:2020-05-20
Applicant: STMicroelectronics (Tours) SAS
Inventor: Ghafour Benabdelaziz , Cedric Reymond
IPC: H03K17/56 , H02M7/06 , H02P27/04 , H02M5/257 , H03K17/725 , H02M1/08 , H02M7/155 , H03K17/722
Abstract: A thyristor or triac control circuit includes a first capacitive element that is series-connected with a first diode between a first terminal and a second terminal intended to be coupled to a gate of the thyristor or triac. A second capacitive element is coupled between the second terminal and a third terminal intended to be connected to a conduction terminal of the thyristor or triac on the gate side of the thyristor or triac. A second diode is coupled between the third terminal and a node of connection of the first capacitive element and first diode.
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