公开(公告)号：US20020125917A1

公开(公告)日：2002-09-12

申请号：US10143417

申请日：2002-05-10

Applicant: STMicroelectronics Limited

Inventor： William Barnes

IPC: H03F003/45

CPC classification number: H03K5/249 ,  H03K3/356139 ,  H03K5/2481

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

Abstract translation: 具有用于比较第一和第二电压的比较装置的比较器电路具有用于向所述比较装置提供电流的电流源电路，所述电流源电路具有用于接收具有第一和第二状态的时钟信号的输入，由此比较装置开始比较 当时钟信号从第一状态转变到第二状态时的第一和第二电压; 以及用于确定何时所述比较装置已经完成了所述第一和第二电压的比较并且用于当所述比较完成时关闭所述电流源电路以及因此所述比较装置的装置。

公开(公告)号：US20040105242A1

公开(公告)日：2004-06-03

申请号：US10714760

申请日：2003-11-17

Applicant: STMicroelectronics Limited

Inventor： Paul Evans

IPC: H05K007/10

CPC classification number: H01R12/523 ,  H05K1/144

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

公开(公告)号：US20030196041A1

公开(公告)日：2003-10-16

申请号：US10446280

申请日：2003-05-23

Applicant: STMicroelectronics Limited

Inventor： Andrew Craig Sturges ,  David May

IPC: G06F012/00

CPC classification number: G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract translation: 提供一种缓存系统，其包括高速缓冲存储器和高速缓冲存储器补充机制，其根据主存储器中的项目的地址将高速缓冲存储器中的一组高速缓存分区中的一个或多个分配给项目。 这在所描述的实施例之一中通过用项目的地址包括一组分区选择器位来实现，所述分组选择器位允许生成分区掩码以识别可以加载该物品的高速缓存分区。

公开(公告)号：US20030182570A1

公开(公告)日：2003-09-25

申请号：US10354891

申请日：2003-01-30

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: G06F011/30

CPC classification number: G06F21/575 ,  G06F21/64

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor.

Abstract translation: 半导体集成电路包括用于从存储器执行应用代码的处理器和被布置为经由与处理器相同的内部总线接收应用代码的验证器处理器。 验证者处理器执行验证功能以检查应用代码是否可信。 验证者处理器自动运行，并且不能通过与主处理器相同的内部总线接收应用代码而被欺骗。

公开(公告)号：US20030107825A1

公开(公告)日：2003-06-12

申请号：US10171453

申请日：2002-06-13

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics Limited

Inventor： Pierangelo Magni ,  Francesco Sala ,  Eric Christison ,  Andrea Giovanni Cigada

IPC: G02B007/02

CPC classification number: G02B7/022 ,  G02B7/04 ,  H01L31/0203 ,  H01L31/02325 ,  H04N5/2253 ,  H04N5/2254

Abstract: An image-detecting device including: a body housing a sensor; a first supporting element, rigidly coupled with the body and defining a seat; and an objective including at least one optical unit having an optical axis. The seat forms a guide portion engaging directly and slidably an alignment portion formed by said optical unit to keep the optical axis orthogonal to the sensor.

Abstract translation: 一种图像检测装置，包括：容纳传感器的主体; 第一支撑元件，与主体刚性联接并且限定座椅; 以及包括具有光轴的至少一个光学单元的目标。 所述座部形成与所述光学单元形成的对准部分直接且可滑动地接合以使光轴正交于所述传感器的引导部。

公开(公告)号：US20030106048A1

公开(公告)日：2003-06-05

申请号：US10103655

申请日：2002-03-20

Applicant: STMicroelectronics Limited

Inventor： Sean McGoogan ,  Richard Shann

IPC: G06F009/45 ,  G06F009/44

CPC classification number: G06F9/45512 ,  G06F9/44521

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module including a plurality of relocation instructions having at least one information output relocation with a field indicating information to be output, the method including reading a relocation instruction from one of the object code modules, and when the read relocation instruction is an information output relocation, displaying the information indicated in the field in a human readable form.

Abstract translation: 一种从多个目标代码模块形成可执行程序的方法，每个目标代码模块包括具有至少一个信息输出重定位的多个重定位指令，其中一个字段指示要输出的信息，该方法包括从一个目标代码模块读取重定位指令 的目标代码模块，并且当读取重定位指令是信息输出重定位时，以人类可读形式显示在该领域中指示的信息。

公开(公告)号：US20020176233A1

公开(公告)日：2002-11-28

申请号：US10085121

申请日：2002-02-27

Applicant: STMicroelectronics Limited

Inventor： Paul Evans

IPC: H05K007/00

CPC classification number: H01R12/523 ,  H05K1/144

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract translation: 一种用于处理器系统的可堆叠模块，其包括具有安装到其顶侧的一组顶侧电路部件的支撑板以及顶侧和下侧连接器。 该模块可与其他这样的模块堆叠并且设置有导电轨道，其被布置成在堆叠中的模块之间传送传输流数据和传输流控制信号。 还提供了处理器系统中的这种模块的堆叠。

公开(公告)号：US20020146130A1

公开(公告)日：2002-10-10

申请号：US10099589

申请日：2002-03-13

Applicant: STMicroelectronics Limited

Inventor： Andrew R. Dellow

IPC: H04L009/00

CPC classification number: H04N21/462 ,  H04N5/76 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/434 ,  H04N21/4408 ,  H04N2005/91364

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

Abstract translation: 用于定位对应于包含在可变可能位置的分组标识（PID）的DES密钥值的设备，该可变位置仅包括32位分组报头的一部分。 存储在存储器中的表包含每个DES密钥：（i）具有32位的分组报头，其中包含在定义的位置处的12,9或8位的PID，并且在其他地方具有零值，以及（ii）掩码值 具有32位，其中包含在PID的所述定义的位置处，并且其他地方具有零。 该表被分成用于相应分组格式类型的区域。 在输入处的输入分组报头与表中的第一个掩码值组合，以提供组合值，该组合值由保存在定义位置的输入分组报头中的值和其他地方的零组成。 将该组合值与存储在表中的相应分组报头进行比较。 当它们不相等时，对于表的下一行重复组合和比较。 当它们相等时，从表中读取相应的DES密钥值作为输出。 该系统可以处理数据包头中的可变PID格式，而不会改变硬件，但只能对表内容进行重新编程。

公开(公告)号：US20040122881A1

公开(公告)日：2004-06-24

申请号：US10632530

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.l.

Inventor： Philip Mattos ,  Marco Losi

IPC: G06F017/15

CPC classification number: G01S19/37 ,  G01S19/24 ,  G01S19/29 ,  G01S19/30 ,  H04B1/708 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，包括两个循环移位寄存器的存储装置循环接收信号的采样，以便与本地生成的GPS码版本相关。 在跟踪模式中，采样信号被直接提供给相关器。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US20040004977A1

公开(公告)日：2004-01-08

申请号：US10421317

申请日：2003-04-22

Applicant: STMicroelectronics Limited

Inventor： William Robbins ,  David Wilkins

IPC: H04J003/04

CPC classification number: H04N21/434

Abstract: There is disclosed a circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data, so as to retain only those parts of the digital data stream required by the receiver. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver. A first control circuit extracts a packet identifier from an input data packet in the digital data stream, and generates a signal in dependence on whether the input data packet is of the first or second type. Sets of information associated with the first types of data packets and required by the receiver are stored in a memory under the control of a second control circuit. A third control circuit, responsive to receipt of the first type of input data packet, determines whether at least part of the input data packet matches the stored sets of information, and sets a match signal responsive thereto.

Abstract translation: 公开了一种用于在接收机中解复用包括至少两种数据的数字数据流的电路和方法，以便仅保留接收机所需的数字数据流的那些部分。 在一个特定应用中，这种接收机用在具有数字机顶盒接收机的电视系统中。 第一控制电路从数字数据流中的输入数据包中提取分组标识符，并根据输入数据分组是第一类还是第二类产生信号。 在第二控制电路的控制下，与第一类型的数据分组相关联并且由接收机所要求的信息集存储在存储器中。 响应于接收到第一类型的输入数据分组的第三控制电路确定输入数据分组的至少一部分是否与存储的信息组匹配，并且响应于此设置匹配信号。