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公开(公告)号：US08314648B2
公开(公告)日：2012-11-20
申请号：US12734394
申请日：2008-09-01
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/077
摘要： An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.
摘要翻译： 本发明的一个实施例提供一种电源电路，其包括使用仅由N沟道晶体管提供的开关元件的电荷泵浦升压器部分，但不具有通过阈值的电压降的问题。 当在升压部中的第一电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第三电容器，进一步升高电压，从而导通第一晶体管。 当在升压部中的第二电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第四电容器，进一步升压电压，从而导通第二晶体管。 这种布置消除了用作输出侧开关元件的第一和第二晶体管中的阈值电压下降的问题。
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12.发明授权Display device having display area and non-display area, and driving method thereof 有权具有显示区域和非显示区域的显示装置及其驱动方法公开(公告)号：US08130216B2
公开(公告)日：2012-03-06
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。
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公开(公告)号：US07659877B2
公开(公告)日：2010-02-09
申请号：US10887308
申请日：2004-07-09
IPC分类号： G09G3/36
CPC分类号： G11C19/28 , G09G3/3677 , G09G3/3688 , G09G2330/021
摘要： A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SL1 through SLn not to overlap each other.
摘要翻译： 移位寄存器包括对应于各个块的控制电路CNi（i = 1至n），并且下一级的电平移位器LSi + 1由移位寄存器的输出之一和触发器的输出之一 Fi。 由此，本阶段的电平移位器仅对于从当前块输出移位输出的期间最小化，从而能够降低功耗。此外，可以使输出SL1〜SLn不与各块重叠 其他。
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公开(公告)号：US20090121998A1
公开(公告)日：2009-05-14
申请号：US12087887
申请日：2006-11-30
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2310/0245 , G09G2310/0286 , G09G2330/027 , G11C19/28
摘要： A liquid crystal display apparatus (1) wherein the shift registers of a source driver (4) are configured by use of asynchronous RS flip-flops in which an active input to a set input terminal has a higher priority than an active input to a reset terminal. In a second mode of operation, first and second clock signals and a start pulse are fixed at high levels, thereby performing discharges from all the pixels (PIX) of a liquid crystal panel (2).
摘要翻译： 一种液晶显示装置（1），其中源驱动器（4）的移位寄存器通过使用异步RS触发器来配置，其中对设置输入端子的有效输入具有比复位的有效输入更高的优先级 终奌站。 在第二操作模式中，第一和第二时钟信号和起始脉冲被固定为高电平，从而执行来自液晶面板（2）的所有像素（PIX）的放电。
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公开(公告)号：US07248243B2
公开(公告)日：2007-07-24
申请号：US10438886
申请日：2003-05-16
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Shunsuke Hayashi , Hajime Washio , Eiji Matsuda , Sachio Tsujino
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Shunsuke Hayashi , Hajime Washio , Eiji Matsuda , Sachio Tsujino
IPC分类号： H03K19/0175 , H03L5/00 , G09G3/28 , G09G3/36 , G09G5/00
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
摘要翻译： 电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。 电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器 输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。 利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。
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公开(公告)号：US07209130B2
公开(公告)日：2007-04-24
申请号：US10941912
申请日：2004-09-16
申请人： Sachio Tsujino , Hoh Riku
发明人： Sachio Tsujino , Hoh Riku
CPC分类号： G09G3/20 , G09G2300/0408 , G09G2310/0267 , G09G2310/0275 , G09G2310/0289
摘要： A level-shifter is combined with a bi-directional shift register. The level shifter turns a start signal of the bi-directional shift register to be an enable signal, and (i) activates a level shifting section by supplying a stationary current, during a period in which the enable signal is HIGH, while (ii) deactivates the level shifting section by cutting off the stationary current, during a period in which the enable signal EN is LOW. With this, it is possible to reduce unnecessary current consumption by a level shifter provided for a signal which does not frequently change, such as a shifting direction switching signal for which the bi-directional shift register is provided. At the same time, when such a signal changes, the change is followed with no time lag.
摘要翻译： 电平移位器与双向移位寄存器组合。 电平移位器将双向移位寄存器的起始信号变为使能信号，（i）在使能信号为高电平的期间通过提供稳定电流来激活电平移位部分，而（ii） 在使能信号EN为低电平的时间段期间，通过切断稳定电流来停止电平转换部分。 由此，可以减少为不频繁变化的信号设置的电平移位器，例如设置有双向移位寄存器的移位方向切换信号来减少不必要的电流消耗。 同时，当这种信号发生变化时，随之而来的是变化，没有时间滞后。
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公开(公告)号：US20070024567A1
公开(公告)日：2007-02-01
申请号：US11543218
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.
摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。
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公开(公告)号：US20050030276A1
公开(公告)日：2005-02-10
申请号：US10887308
申请日：2004-07-09
CPC分类号： G11C19/28 , G09G3/3677 , G09G3/3688 , G09G2330/021
摘要： A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SL1 through SLn not to overlap each other.
摘要翻译： 移位寄存器包括对应于各个块的控制电路CNi（i = 1至n），并且下一级的电平移位器LSi + 1由移位寄存器的输出之一和触发器的输出之一 Fi。 由此，本阶段的电平移位器仅对于从当前块输出移位输出的期间最小化，从而能够降低功耗。此外，可以使输出SL1〜SLn不与各块重叠 其他。
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公开(公告)号：US20050017942A1
公开(公告)日：2005-01-27
申请号：US10895891
申请日：2004-07-22
申请人： Sachio Tsujino , Shinya Takahashi
发明人： Sachio Tsujino , Shinya Takahashi
CPC分类号： G09G3/20 , G09G2310/0267 , G09G2310/08 , G09G2330/021
摘要： A display device is provided with a shift register having a plurality of bistable circuits, each of the bistable circuits being connected to a corresponding scanning line. An RS flip-flop circuit provided in each of the bistable circuits functions as a memory portion for discriminating a start position of a display region for partial display. When partial display is carried out, first, only the RS flip-flop circuit corresponding to the start position of the display region is put into the set state, that is, only the bistable circuit corresponding to the start position of the display region is put into the set state. Moreover, the scanning lines that are connected to the bistable circuits from the start position to the end position are driven sequentially. During this, only the bistable circuit corresponding to the start position is kept in the set state, and the other bistable circuits are kept in the reset state.
摘要翻译： 显示装置设置有具有多个双稳态电路的移位寄存器，每个双稳态电路连接到相应的扫描线。 设置在每个双稳态电路中的RS触发器电路用作用于区分用于部分显示的显示区域的开始位置的存储部分。 当进行部分显示时，首先，仅将与显示区域的开始位置相对应的RS触发器电路置于设定状态，即仅放置与显示区域的开始位置对应的双稳态电路 进入设定状态。 此外，从起始位置到结束位置连接到双稳态电路的扫描线被依次驱动。 在此期间，只有与开始位置相对应的双稳电路保持在设定状态，其他双稳态电路保持在复位状态。
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公开(公告)号：US20120313913A1
公开(公告)日：2012-12-13
申请号：US13581208
申请日：2010-11-24
IPC分类号： G09G5/00
CPC分类号： G06K9/0004 , G06F3/0412 , G06K9/00013 , G09G3/3648 , G09G2300/0426 , G09G2360/144 , G09G2360/147
摘要： Detection signals of respective photo sensor circuits (senS, senD, senON, and senOFF) are activated so as to be output at once for each group of prescribed plural number of sensor rows (LSk) by a row driver (6). Within the prescribed number of sensor rows (LSk), photo sensor circuits (senS, senD, senON, and senOFF) sharing the same power line (SL2, SL5, . . . ) between at least two different sensor rows (LSk) are included. The detection signals of the respective photo sensor circuits (senS, senD, senON, and senOFF) in the prescribed number of sensor rows (senS, senD, senON, and senOFF) are output via mutually different output lines (SL1/SL3, SL4/SL6, . . . ).
摘要翻译： 各光电传感器电路（senS，senD，senON，senOFF）的检测信号被激活，以便通过行驱动器（6）为每组规定的多个传感器行（LSk）一次输出。 在规定数量的传感器行（LSk）内，包括在至少两个不同传感器行（LSk）之间共享同一电力线（SL2，SL5 ...）的光电传感器电路（senS，senD，senON和senOFF） 。 在规定数量的传感器列（senS，senD，senON和senOFF）中的各个光电传感器电路（senS，senD，senON和senOFF）的检测信号通过相互不同的输出线（SL1 / SL3，SL4 / SL6，...）。
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