Abstract:
The overall architecture and details of a scalable video fingerprinting and identification system that is robust with respect to many classes of video distortions is described. In this system, a fingerprint for a piece of multimedia content is composed of a number of compact signatures, along with traversal hash signatures and associated metadata. Numerical descriptors are generated for features found in a multimedia clip, signatures are generated from these descriptors, and a reference signature database is constructed from these signatures. Query signatures are also generated for a query multimedia clip. These query signatures are searched against the reference database using a fast similarity search procedure, to produce a candidate list of matching signatures. This candidate list is further analyzed to find the most likely reference matches. Signature correlation is performed between the likely reference matches and the query clip to improve detection accuracy.
Abstract:
An architecture for a multimedia search system is described. To perform similarity matching of multimedia query frames against reference content, reference database comprising of a cluster index using cluster keys to perform similarity matching and a multimedia index to perform sequence matching is built. Methods to update and maintain the reference database that enables addition and removal of the multimedia contents, including portions of multimedia content, from the reference database in a running system are described. Hierarchical multi-level partitioning methods to organize the reference database are presented. Smart partitioning of the reference multimedia content according to the nature of the multimedia content, and according to the popularity among the social media, that supports scalable fast multimedia identification is also presented. A caching mechanism for multimedia search queries in a centralized or in a decentralized distributed system and a client based local multimedia search system enabling multimedia tracking are described.
Abstract:
A jitter buffer receives a plurality of data packets comprising a circuit emulation service over internet protocol (CESIP), buffers the plurality of data packets, and plays data from the plurality of data packets at a constant bit rate corresponding to the CESIP.
Abstract:
A micro-programmable controller is disclosed for parsing a packet and encapsulating data to form a packet. The micro-programmable controller loads an instruction within the micro-controller. The instruction word has a plurality of instruction fields. The micro-controller processes the plurality of instruction fields in parallel. Each instruction field is related to a specific operation for parsing a packet or encapsulating data to form a packet. The programmable micro-controller can be programmed to handle packets to support new types of protocols by programming a template to string specific routines together based on an instruction set specific for parsing and encapsulating.
Abstract:
A jitter buffer receives a plurality of data packets comprising a circuit emulation service over internet protocol (CESIP), buffers the plurality of data packets, and plays data from the plurality of data packets at a constant bit rate corresponding to the CESIP.
Abstract:
A jitter buffer receives a plurality of data packets comprising a circuit emulation service over internet protocol (CESIP), buffers the plurality of data packets, and plays data from the plurality of data packets at a constant bit rate corresponding to the CESIP.
Abstract:
A novel system and method of monitoring network activity in a network switching system having multiple ports for receiving and transmitting data packets, and a decision making engine for controlling data forwarding between the ports. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a predetermined algorithm to determine destination information. At least one port for transmitting data packets is identified based on the destination information. In addition, a sniffer port selected among the plurality of ports is identified as a transmit port to provide output of data packets received or transmitted by multiple sniffed ports. A traffic capture mechanism that enables the sniffer port to output data transferred via multiple sniffed ports includes a sniffer port configuration circuit for selecting the sniffer port, and a sniffed port configuration circuit for selecting the multiple sniffed ports. The sniffer port configuration circuit may provide a signal to enable or disable monitoring of data traffic on the multiple sniffed ports.
Abstract:
A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding decisions. The switch buffers data frame header information in an internal memory for processing by the decision making logic. The switch employs a modular architecture that enables the decision making logic to perform its processing independently from other logic functions of the switch.
Abstract:
A test system includes a switch emulator, a network test device, and an interface converter. The switch emulator is configured for transmitting first network data on a first media independent interface based on a first interface clock, and the network test device configured for transmitting second network data on a second media independent interface based on a second interface clock. The interface converter, having inverted media independent interfaces, is configured for transferring the first and second network data between the first and second media independent interfaces, and supplying the first and second interface clocks based on an external clock generated by the switch emulator. Hence, network data can be passed between the switch emulator and the network test device according to network protocols, even if the switch emulator is operating at relatively slow speeds.
Abstract:
Multiple network switches are configured having memory interfaces that transfer segmented packet data to each other via a unidirectional data bus ring connecting the network switches in a single ring or “daisy chain” arrangement. The memory interfaces are also configured for transferring the segmented packet data to respective local buffer memories for temporary storage. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by requiring only one read and one write operation to and from the local buffer memory for each segmented packet data being received and transmitted through the switches.