公开(公告)号：US20090065945A1

公开(公告)日：2009-03-12

申请号：US12208200

申请日：2008-09-10

Applicant: Si Woo Lee

Inventor： Si Woo Lee

IPC: H01L23/48

CPC classification number: H01L23/522 ,  H01L23/585 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0288 ,  H01L2924/14

Abstract: A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an entirety and a portion of the plurality of metal lines included in the buffer area forms protective resistance interconnecting the input/output pad to the input line.

Abstract translation: 半导体器件包括输入/​​输出焊盘，内部电路的输入线和形成在输入/输出焊盘的下部上的多条金属线，以具有与输入/输出的平面区域重叠的缓冲区域 衬垫，其中包括在缓冲区域中的多个金属线的整体和一部分中的一个形成将输入/输出焊盘互连到输入线的保护电阻。

公开(公告)号：US20090065837A1

公开(公告)日：2009-03-12

申请号：US12264490

申请日：2008-11-04

Applicant: Jung-Hwa LEE ,  Si-Woo LEE

Inventor： Jung-Hwa LEE ,  Si-Woo LEE

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/40

Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.

Abstract translation: 提供了具有外围电路电容器的半导体存储器件。 在半导体存储器件中，第一节点电连接到外围电路区域中的多个电容器的多个下电极，以平行地连接至少一部分电容器。 第二节点电连接到外围电路区域中的电容器的多个上电极，以平行地连接至少一部分电容器。 第一节点形成在与单元阵列区域中的位线基本相同的电平上，并且由用于形成位线的相同材料形成。

公开(公告)号：US20070242401A1

公开(公告)日：2007-10-18

申请号：US11735038

申请日：2007-04-13

Applicant: Jung Eon MOON ,  Dae Gwan KANG ,  Kook Whee KWAK ,  Nak Heon CHOI ,  Si Woo LEE ,  Hee Jeong SON ,  Suk YUN ,  Seong Hoon JEONG ,  Joon Won LEE

Inventor： Jung Eon MOON ,  Dae Gwan KANG ,  Kook Whee KWAK ,  Nak Heon CHOI ,  Si Woo LEE ,  Hee Jeong SON ,  Suk YUN ,  Seong Hoon JEONG ,  Joon Won LEE

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.

Abstract translation: 静电放电（ESD）保护电路保护内部电路中元件的栅极氧化物免受ESD影响。 在ESD测试期间，如果连接在电源焊盘和接地焊盘之间的ESD保护器的驱动电压的总和高于内部电路中的元件的栅极氧化物击穿电压，则ESD保护器的结构被改变，或者另一个ESD保护器 另外设置为保护内部电路中的元件的栅极氧化物免于ESD。