公开(公告)号：US20040003178A1

公开(公告)日：2004-01-01

申请号：US10187072

申请日：2002-07-01

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F012/02

CPC classification number: G06F12/0875 ,  G06F12/0862

Abstract: Methods and apparatus enable: the partitioning of a main memory into a plurality of blocks, each block being adjacent to at least one of the other blocks, and each block including a plurality of data units containing one or more bits of data; the partitioning of each block of the main memory into a plurality of zones, each zone containing one or more of the data units; the association of at least some of the respective zones of each given block with respective others of the adjacent blocks to the given block; and the pre-fetching of a given one of the other blocks into a cache memory when any one of the data units within any of the associated zones of that block is addressed.

Abstract translation: 方法和装置使得能够将主存储器划分成多个块，每个块与至少一个其它块相邻，并且每个块包括包含一个或多个数据位的多个数据单元; 将主存储器的每个块划分成多个区域，每个区域包含一个或多个数据单元; 每个给定块的相应区域中的至少一些区域与相邻块的相应块的关联到给定块; 以及在该块的任何相关联的区域内的任何一个数据单元被寻址时，将其他块中的给定一个块预取入高速缓冲存储器。

公开(公告)号：US20030208661A1

公开(公告)日：2003-11-06

申请号：US10187150

申请日：2002-07-01

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F012/00

CPC classification number: G06F9/3824 ,  G06F9/30043 ,  G06F9/3885 ,  G06F12/0888 ,  G06F12/126 ,  G06F12/127

Abstract: Methods and apparatus for controlling a cache memory are described in which the overwriting of floating point data into any cache line of the cache memory is prohibited when the data stored in such cache line are valid, integer data.

Abstract translation: 描述了用于控制高速缓冲存储器的方法和装置，其中当存储在这种高速缓存行中的数据有效时，将浮点数据重写到高速缓存存储器的任何高速缓存行中是有效的，整数数据。

公开(公告)号：US20030196102A1

公开(公告)日：2003-10-16

申请号：US10123923

申请日：2002-04-16

Applicant: Sony Computer Entertainment America Inc.

Inventor： William M. McCarroll

IPC: H04L009/00

CPC classification number: G06F21/123 ,  G06F21/51

Abstract: A system includes an associated tamperproof circuit that contains a cryptography unit and one or more keys. The system receives software having one or more portions of code that have been digitally signed prior to receipt of the code by the system. The cryptography unit and one of the keys contained in the tamperproof circuit are used to decrypt a signature file for a portion of the code. The validity of the portion of code is determined by using the decrypted signature file, and if the portion of code is invalid, operation of the system is prevented. One or more portions of the code received by the system, such as a communications protocol, may also be encrypted prior to receipt of the code by the system. The system obtains a key from a remote server via a secure communications channel and uses the key and the cryptography unit contained in the tamperproof circuit to decrypt the communications protocol. The system then uses the communications protocol to communicate across a network with another client, such as to play an online game.

Abstract translation: 系统包括相关联的防篡改电路，其包含密码单元和一个或多个密钥。 在系统接收到代码之前，该系统接收具有已被数字签名的一个或多个代码部分的软件。 密码单元和包含在防篡改电路中的键之一用于对代码的一部分的签名文件进行解密。 通过使用解密的签名文件来确定代码部分的有效性，并且如果代码部分无效，则防止系统的操作。 系统接收到的代码（例如通信协议）的一个或多个部分也可以在系统接收到代码之前进行加密。 系统通过安全通信通道从远程服务器获取密钥，并使用防篡改电路中包含的密钥和密码单元对通信协议进行解密。 系统然后使用通信协议通过网络与另一个客户端进行通信，例如播放在线游戏。

公开(公告)号：US20130304931A1

公开(公告)日：2013-11-14

申请号：US13941436

申请日：2013-07-12

Applicant: Sony Computer Entertainment America, Inc.

Inventor： Mark Lester Jacob ,  Ronald Joseph Roy ,  Adam Pierce Harris

IPC: H04L29/06

CPC classification number: H04L65/1066 ,  H04L29/12528 ,  H04L61/2575 ,  H04L63/029 ,  H04L67/101 ,  H04L67/1034 ,  H04L67/104 ,  H04L67/1051 ,  H04L67/1093 ,  H04L67/34 ,  H04L69/24 ,  H04L69/40

Abstract: Systems and methods of the present invention for maintaining network data distribution are provided. Network data may be distributed in such as manner as to allow a network session to weather interrupted communications between host and clients without significant loss of data. Embodiments of the present invention provide for one or more clients to serve as backup host(s) for the network session, such determinations including the use of NAT profile information. When the other clients transmit data to the host, they may also transmit the data to one or more backup hosts if there are any indications of interrupted communication.

Abstract translation: 提供了用于维护网络数据分布的本发明的系统和方法。 网络数据可以以允许网络会话在主机和客户端之间中断通信而不显着数据丢失的方式来分发。 本发明的实施例提供一个或多个客户端用作网络会话的备份主机，这样的确定包括使用NAT简档信息。 当其他客户端向主机发送数据时，如果有任何中断通信的指示，它们也可以将数据发送到一个或多个备份主机。

公开(公告)号：US20030177343A1

公开(公告)日：2003-09-18

申请号：US10202355

申请日：2002-07-24

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F009/00

CPC classification number: G06F15/8053 ,  A63F2300/203 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3885

Abstract: A multi-processing computer architecture and a method of operating the same are provided. The multi-processing architecture provides a main processor and multiple sub-processors cascaded together to efficiently execute loop operations. The main processor executes operations outside of a loop and controls the loop. The multiple sub-processors are operably interconnected, and are each assigned by the main processor to a given loop iteration. Each sub-processor is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor.

Abstract translation: 提供了多处理计算机体系结构及其操作方法。 多处理架构提供了主处理器和多个子处理器级联在一起以有效地执行循环操作。 主处理器执行循环外的操作并控制循环。 多个子处理器可操作地互连，并且由主处理器分配给给定的循环迭代。 每个子处理器可操作以顺序地接收一个或多个子指令，对每个子指令进行操作，并将子指令传播到后续的子处理器。

公开(公告)号：US20020190775A1

公开(公告)日：2002-12-19

申请号：US10113052

申请日：2002-04-01

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F001/04

CPC classification number: G06F1/10

Abstract: A semiconductor device includes a transmission line bounded by a first buffer and a second buffer. The first and second buffers are placed such that the transmission line has a length between a minimum and a maximum, thereby permitting narrow clock signal pulses to be transmitted with reduced distortion.

Abstract translation: 半导体器件包括由第一缓冲器和第二缓冲器限定的传输线。 放置第一和第二缓冲器使得传输线具有最小和最大值之间的长度，从而允许以较小的失真传输窄时钟信号脉冲。