公开(公告)号：US20090110130A1

公开(公告)日：2009-04-30

申请号：US12112152

申请日：2008-04-30

申请人： James Boomer ,  Oscar Freitas ,  Steven Macaluso

发明人： James Boomer ,  Oscar Freitas ,  Steven Macaluso

IPC分类号： H04L7/00

CPC分类号： H04B3/30

摘要： A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

摘要翻译： 用于消除彼此通信的逻辑系统之间的控制线的系统和过程。 在一个实施例中，系统向接收机发送指示第一模式的频率。 在第一模式中，可以发送第一数据类型。 当频率改变时，指示可以发送第二数据类型的第二模式。 接收机检测频率变化并采取所指示的第一或第二模式。

公开(公告)号：US20070057713A1

公开(公告)日：2007-03-15

申请号：US11226031

申请日：2005-09-14

申请人： Steven Macaluso

发明人： Steven Macaluso

IPC分类号： H03K3/00

CPC分类号： H03K5/1515 ,  H03K5/15

摘要： An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steering FET controlled by an input signal drives a first output high via a circuit. That first output going high, after a delay, drives a second output high. When the input goes low, a second steering FET controlled by the input signal drives the second output low. That second output going low, after a delay, drives the first output low. No latching is provided in the present invention.

摘要翻译： 公开了一种包络曲线发生器，其确保当两个曲线都从一个逻辑电平运行到另一个逻辑电平时，一个曲线将包围或重叠另一个曲线，并且当两个曲线都横过另一个方向时，另一个重叠。 在一种情况下，由输入信号控制的转向FET通过电路驱动第一输出高电平。 第一个输出高一点，经过一段延迟，推动了第二个输出高。 当输入变低时，由输入信号控制的第二转向FET驱动第二输出为低电平。 第二个输出为低电平，延迟后驱动第一个输出为低电平。 在本发明中没有提供闩锁。

公开(公告)号：US20130265184A1

公开(公告)日：2013-10-10

申请号：US13860203

申请日：2013-04-10

申请人： John L. Carpentier ,  Julie Lynn Stultz ,  Steven Macaluso

发明人： John L. Carpentier ,  Julie Lynn Stultz ,  Steven Macaluso

IPC分类号： H03M1/34 ,  H03M1/12

CPC分类号： H03M1/34 ,  H03K17/163 ,  H03K2217/0054 ,  H03M1/12

摘要： This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds.

摘要翻译： 本文件尤其涉及包括被配置为接收使能信号并向控制逻辑提供ADC输出信号的模拟 - 数字控制器（ADC）的装置和方法，其中所述控制逻辑被配置为提供控制电压 到开关的控制输入。 在一个示例中，当ADC输出信号低于第一阈值或高于第二阈值时，控制电压包括ADC输出信号。 在某些示例中，当ADC输出信号在第一和第二阈值之间时，控制逻辑被配置为将控制电压从第一阈值转换到第二阈值。

公开(公告)号：US08502595B2

公开(公告)日：2013-08-06

申请号：US13428218

申请日：2012-03-23

申请人： Julie Lynn Stultz ,  James Joseph Morra ,  Steven Macaluso

发明人： Julie Lynn Stultz ,  James Joseph Morra ,  Steven Macaluso

IPC分类号： H03K17/56

CPC分类号： H03K17/687 ,  H03K17/145 ,  H03K2017/6875 ,  H03K2217/0036 ,  H03K2217/0054

摘要： This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

摘要翻译： 本文件尤其讨论了用于在掉电状态下传递信号的装置和方法。 示例性开关器件可以包括第一耗尽型晶体管，其被配置为在第一状态下在第一节点和第二节点之间传递模拟信号，并且在第二状态下将第一节点与第二节点隔离，控制电路耦合到 所述第一耗尽型晶体管的控制节点被配置为将所述控制节点与处于所述第一状态的第一电源输入隔离，并且在所述第二状态下将所述控制节点耦合到所述第一电源输入;以及跟踪电路， 在第一状态期间将第一耗尽型晶体管的控制节点连接到第一节点，并且在第二状态下将第一耗尽型晶体管的控制节点与第一节点隔离。

公开(公告)号：US20120242397A1

公开(公告)日：2012-09-27

申请号：US13428218

申请日：2012-03-23

申请人： Julie Lynn Stultz ,  James Joseph Morra ,  Steven Macaluso

发明人： Julie Lynn Stultz ,  James Joseph Morra ,  Steven Macaluso

IPC分类号： H03K17/687

CPC分类号： H03K17/687 ,  H03K17/145 ,  H03K2017/6875 ,  H03K2217/0036 ,  H03K2217/0054

摘要： This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

摘要翻译： 本文件尤其讨论了用于在掉电状态下传递信号的装置和方法。 示例性开关器件可以包括第一耗尽型晶体管，其被配置为在第一状态下在第一节点和第二节点之间传递模拟信号，并且在第二状态下将第一节点与第二节点隔离，控制电路耦合到 所述第一耗尽型晶体管的控制节点被配置为将所述控制节点与处于所述第一状态的第一电源输入隔离，并且在所述第二状态下将所述控制节点耦合到所述第一电源输入;以及跟踪电路， 在第一状态期间将第一耗尽型晶体管的控制节点连接到第一节点，并且在第二状态下将第一耗尽型晶体管的控制节点与第一节点隔离。

公开(公告)号：US20110255203A1

公开(公告)日：2011-10-20

申请号：US12760286

申请日：2010-04-14

申请人： Julie Lynn Stultz ,  Nickole Gagne ,  Steven Macaluso

发明人： Julie Lynn Stultz ,  Nickole Gagne ,  Steven Macaluso

IPC分类号： H02H3/00

CPC分类号： H03K17/063 ,  H03K3/356113 ,  H03K2017/066 ,  H03K2217/0054 ,  H03K2217/0081

摘要： This application discusses, among other things, switch circuit apparatus having power down protection and not requiring power up sequencing. An apparatus embodiment can include a first supply node coupled to a first input of a level shifting circuit via a protection circuit, a second supply node coupled to a second input of the level shifting circuit via a single pull-up transistor, and a switch including a control input, a first node, and a second node controllably isolated from the first node, wherein the control input is coupled to the level shifting circuit. The first and second inputs of the level shifting circuit can be coupled via a rectifier, and the protection circuit can be configured to power the first and second supply nodes to controllably isolate the first and second nodes from each other when a voltage of one of the first or second nodes exceeds a threshold.

摘要翻译： 除了别的以外，本申请还讨论了具有掉电保护并且不需要上电排序的开关电路装置。 装置实施例可以包括经由保护电路耦合到电平移位电路的第一输入的第一电源节点，经由单个上拉晶体管耦合到电平移位电路的第二输入的第二电源节点，以及包括 控制输入​​，第一节点和与第一节点可控地隔离的第二节点，其中控制输入耦合到电平移位电路。 电平移位电路的第一和第二输入可以经由整流器耦合，并且保护电路可以被配置为对第一和第二电源节点供电，以便当第一和第二电源节点之一的电压 第一或第二节点超过阈值。